CS4461 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CS4461 Datasheet PDF : 11 Pages
| |||
4. APPLICATIONS
CS4461
4.1 Digital Connections
PSR_MCLK provides the system clock for the CS4461. PSR_SYNC and PSR_DATA provide the output of
the modulator to the class-D modulator with feedback capabilities. Series damping resistors should be used
on PSR_MCLK, PSR_SYNC, and PSR_DATA to minimize noise. These should be placed as close as pos-
sible to their signal source. The pin labeled TEST should also be pulled low to GND through a 47 kΩ resistor
to minimize noise coupling into the ADC modulator.
4.2 Analog Connections
The analog modulator samples the input at PSR_MCLK/4 (6.144 MHz with PSR_MCLK=24.576 MHz).
Figure 2 shows the suggested analog input filter. This filter topology will correctly buffer the power supply’s
AC and DC components for PSR processing by the class-D modulator. The use of capacitors which have a
large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade sig-
nal linearity. C0G dielectrics should be used wherever possible. R1 and R2 should be used to scale VP
(class-D amplifier high voltage power supply) to less than the CS4461 maximum AIN+/AIN- input voltage
(3.9 V).
2 kΩ
2 kΩ
120 pF
VP
+5.0 V
R1
+
R2
-
90.9 Ω
+5.0 V
-
649 Ω
+
90.9 Ω
AIN+
120 pF
2200 pF
C0G
CS4461
649 Ω
AIN-
Figure 2. CS4461 Recommended Analog Input Buffer
The following equation can be used to scale R1 and R2:
2 * (VP * (1 + %VP_Ripple)) * (R2 / (R1 + R2)) < 3.9 V
Example (VP = 40 V, %VP_Ripple = 4%):
2 * (40 * (1 + 0.04)) * (1.96 kΩ / (40.2 kΩ + 1.96 kΩ) = 3.87 V
8
DS650F1
Share Link: 