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CS485NI-XYZR View Datasheet(PDF) - Cirrus Logic

Part Name
Description
Manufacturer
CS485NI-XYZR
Cirrus-Logic
Cirrus Logic Cirrus-Logic
CS485NI-XYZR Datasheet PDF : 26 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
CS485xx Family Data Sheet
32-bit Audio Decoder DSP Family
4.2.5 PLL-based Clock Generator
The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used
to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock
domain can be output on the DAO port for driving audio converters. The CS485xx defaults to running
from the external reference frequency and is switched to use the PLL output after overlays have
been loaded and configured, either through master boot from an external FLASH or through host
control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output
frequency ratio is selectable between 1:1 (default) or 2:1.
4.2.6 Hardware Watchdog Timer
The CS485xx has an integrated watchdog timer that acts as a “health” monitor for the DSP. The
watchdog timer must be reset by the DSP before the counter expires, or the entire chip is reset. This
peripheral ensures that the CS485xx will reset itself in the event of a temporary system failure. In
T stand-alone mode (that is, no host MCU), the DSP will reboot from external FLASH. In slave mode
F (that is, host MCU present) a GPIO will be used to signal the host that the watchdog has expired and
the DSP should be rebooted and re-configured.
A 4.3 DSP I/O Description
R 4.3.1 Multiplexed Pins
Many of the CS485xx family pins are multi-functional. For details on pin functionality please refer to
D the CS485xx Hardware User’s Manual.
4.3.2 Termination Requirements
L I Open-drain pins on the CS485xx must be pulled high for proper operation. Please refer to the
CS485xx Hardware User’s Manual to identify which pins are open-drain and what value of pull-up
IA H resistor is required for proper operation.
Mode select pins in the CS485xx family are used to select the boot mode upon the rising edge from
T P reset. A detailed explanation of termination requirements for each communication mode select pin
N L can be found in the CS485xx Hardware User’s Manual.
4.3.3 Pads
E E The CS485xx I/Os operate from the 3.3 V supply and are 5 V tolerant.
ID D 4.4 Application Code Security
The external program code may be encrypted by the programmer to protect any intellectual property
it may contain. A secret, customer-specific key is used to encrypt the program code that is to be
CONF stored external to the device. Please contact your local Cirrus representative for details.
DS734F2
©Copyright 2008 Cirrus Logic, Inc.
9
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