CDB5339 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CDB5339 Datasheet PDF : 34 Pages
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CS5336, CS5338, CS5339
L/ R
Output
* SCLK
Output
FSYNC
Output
0123
16 17 18 19 20 21 31 0 1 2 3
16 17 18 19 20 21 31 0 1
SDATA
Output
15 14
1 0 T2 T1 T0
15 14
1 0 T2 T1 T0
* SCLK for CS5336/8.
SCLK inverted for
CS5339
Left Audio Data Tag Bits Left Data Tag Right Audio Data Tag Bits
Figure 3. Data Output Timing - MASTER mode
Right Data Tag
L/ R
Input
* SCLK
Input
012
FSYNC
Input (high)
15 16 17 18 19 20 30 31 0 1 2
15 16 17 18 19 20 21 31 0 1
SDATA
Output
15 14 1 0 T2 T1 T0
15 14
1 0 T2 T1 T0
* SCLK for CS5336/8.
SCLK inverted for
CS5339
Left Audio Data Tag Bits Left Data Tag Right Audio Data Tag Bits
Figure 4. Data Output Timing - SLAVE Mode, FSYNC high
Right Data Tag
low, ICLKD is divided by 2 to generate OCLKD.
The phase relationship between ICLKD and
OCLKD is always the same, and is shown in the
Switching Characteristics Timing Diagrams.
When CMODE is high, OCLKD is ICLKD di-
vided by 3. There are two possible phase
relationships between ICLKD and OCLKD,
which depend on the start-up timing between
DPD and L/R, shown in Figure 2.
Serial Data Interface
The serial data output interface has 3 possible
modes of operation: MASTER mode, SLAVE
mode with FSYNC high, and SLAVE mode with
FSYNC controlled. In MASTER mode, the A/D
3-46
converter is driven from a master clock (ICLKD)
and outputs all other clocks, derived from ICLKD
(see Figure 3). Notice the one SCLK cycle delay
between L/R edges and FSYNC rising edges.
FSYNC brackets the 16 data bits for each chan-
nel.
In SLAVE mode, L/R and SCLK are inputs. L/R
must be externally derived from ICLKD, and
should be equal to the Output Word Rate. SCLK
should be equal to the input sample rate, which is
equal to OCLKD/2. Other SCLK frequencies are
possible, but may degrade dynamic range because
of interference effects. Data bits are clocked out
via the SDATA pin using the SCLK and L/R in-
puts. The rising edge of SCLK causes the ADC to
DS23F1
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