CDB5366(2007) View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CDB5366 Datasheet PDF : 41 Pages
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CS5366
SERIAL AUDIO INTERFACE - I²S/LJ TIMING
The serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT.
Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 20 pF, timing threshold is 50% of VLS.
Parameter
Symbol Min
Typ
Sample Rates
Single-Speed Mode
2
Double-Speed Mode
-
54
-
Quad-Speed Mode
108
Master Mode
SCLK Frequency
-
64*Fs
-
SCLK Period
1/(64*216 kHz) tPERIOD
72.3
-
SCLK Duty Cycle (Note 1)
(CLKMODE = 0)(Note 2) tHIGH
40
50
(CLKMODE = 1)(Note 2)
tHIGH
28
33
LRCK setup
LRCK hold
SDOUT setup
SDOUT hold
Slave Mode
before SCLK rising
after SCLK rising
before SCLK rising
after SCLK rising (VLS = 1.8 V)
after SCLK rising (VLS = 3.3 V)
after SCLK rising (VLS = 5 V)
SCLK Frequency (Note 3)
SCLK Period
SCLK Duty Cycle
1/(64*216 kHz)
LRCK setup
LRCK hold
before SCLK rising
after SCLK rising
SDOUT setup
SDOUT hold
before SCLK rising (VLS = 1.8 V)
before SCLK rising (VLS = 3.3 V)
before SCLK rising (VLS = 5 V)
after SCLK rising (VLS = 1.8 V)
after SCLK rising (VLS = 3.3 V)
after SCLK rising (VLS = 5 V)
tSETUP1
tHOLD1
tSETUP2
tHOLD2
tHOLD2
tHOLD2
-
tPERIOD
tHIGH
tSETUP1
tHOLD1
tSETUP2
tSETUP2
tSETUP2
tHOLD2
tHOLD2
tHOLD2
20
20
10
20
10
5
-
72.3
28
20
20
4
10
10
20
10
5
-
-
64*Fs
-
-
-
-
Max
54
108
216
Unit
kHz
64*Fs
Hz
-
ns
60
%
38
%
-
ns
-
ns
-
Hz
-
ns
65
%
-
ns
-
ns
Notes:
1. Duty cycle of generated SCLK depends on duty cycle of received MCLK as specified under “System
Clocking” on page 10.
2. CLKMODE functionality described in Section 4.6.3 "Master Mode Clock Dividers" on page 24.
3. In Slave Mode, the SCLK/LRCK ratio can be set according to preference. However, chip performance
is guaranteed only when using the ratios in Section 4.7 Master and Slave Clock Frequencies on page
25.
SCLK
LRCK
tHOLD1
channel
tPERIOD
tSET UP1
channel
tHIGH
SDOUT
data
tSET UP2
data
tHOLD2
Figure 3. I²S/LJ Timing
DS626F2
15
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