CS7666 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS7666

Digital Color-Space Processor for CCD Cameras

Cirrus Logic 

CS7666

Individual Timing and Synchronization

Signals

In addition to the embedded EAV and SAV timing

signals, the CS7666 provides individual synchroni-

zation output signals which are employed by many

video encoder circuits. These synchronization sig-

nals are typically used to interface the ITU-656 dig-

ital video stream to other components and

subsystems. The individual synchronization sig-

nals include HREFOUT and VREFOUT.

HREFOUT/HSYNC

HREFOUT is an active-high signal indicating

when active pixel data is being transmitted on

DOA[9:0] or DOB[9:0]. HREFOUT is low when

non-active picture data is being transmitted during

horizontal blanking. Depending on the mode of op-

eration, the HREFOUT signal follows either the

HREFIN signal or the HREF defined by the EAV

and SAV code.

The HREFOUT pin may also be configured to pro-

vide a HSYNC output that provides an active low

pulse for 64 pixel clocks whose falling edge occurs

16 pixel clocks after the end of active video for

NTSC (12 clocks for PAL) as per the ITU-R

BT.601 specification. HSYNC is chosen by setting

the Operation Control Register II (07h) HS_SEL

bit (bit 0) to a value of 1. This pin may be inverted

by setting the H_INV bit (register 07h bit2) to a

value of 1. The HSYNC signal may be delayed by

0, 0.5, 1, or 1.5 pixel clocks by setting H_SFT[1-0]

appropriately (register 07h bits 5 and 4.)

VREFOUT/VSYNC

VREFOUT is an output signal that is active high

when the CS7666 is putting out active video lines.

The active-low portion of this signal defines the

vertical blanking period. If the VS_SEL bit in reg-

ister 07h is set, this output pin produces a vertical

sync signal that is compatible with current PAL or

NTSC analog systems. See Figure 4. This signal is

active for 3 line times in NTSC mode (bit 5 of reg-

ister 04h = 0) and 2.5 line times in PAL mode (bit5

of register 04h = 1.) This line may be inverted by

setting the V_INV bit (register 07h) to a value of 1.

Alternately, when the ZV mode bit in register 06h

is set, this output behaves as a VSYNC signal ap-

propriate for ZV ports. In the ZV mode, the

VSYNC signal is active-high during the first six

horizontal line periods of every field. The transition

in VSYNC signal lags the HREF signal’s rising

edge during odd fields and leads the rising edge of

HREF during even fields.

Digital Output Formats

The CS7666 outputs data in a 20-Bit wide format at

the output pixel clock rate. Alternately, the data can

be multiplexed in a 10-bit format at a 2x output pix-

el clock rate. Figures 5 and 6 detail the clock and

data relationships. The output data transitions on

the falling edge of the clock such that the rising

edge of the clock can be used to latch the data into

subsequent circuitry.

The CS7666 delivers 4:2:2 component digital vid-

eo output data in YCrCb format. The data conforms

to the ITU-R BT.656 specification. The Y compo-

nent range is 16-235 (8-bit data) and the Cr and Cb

component ranges are 16-240 (8-bit data). Howev-

er, by setting CLIP_OFF (register 07h bit 6) to a

value of 1, the output data can be extended to a

range of 1-254 (8-bit data). Only 00 and FF are re-

stricted to allow digital timing codes.

The digital outputs can be configured for 10-bit in-

terleaved Y and CrCb data, or for 20-bit parallel

operation. The INTERL bit of the Operational Con-

trol Register 06h determines which output format is

active. Logic 0 places the CS7666 in interleave

mode with output data on channel "A." Logic 1

places the CS7666 in non-interleaved mode where

luminance data is output on channel "A" and

chrominance data is output on channel "B."

DS302PP1

11

Share Link: