CS7666 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS7666

Digital Color-Space Processor for CCD Cameras

Cirrus Logic 

CS7666

GENERAL DESCRIPTION

Overview

The CS7666 forms the heart of a four chip digital

CCD Camera. The four chips include the CCD im-

ager, the CS7615 CCD digitizer, the CS7666 color

space processor, and a vertical drive interface-chip

for the CCD imager. Most four-phase CCD imag-

ers (and their associated vertical drives) can be

used with the CS7615 digitizer and the CS7666

processor to form a simple and cost-effective

YCrCb output format digital camera. The CS7615

and CS7666 together support imager formats rang-

ing from 175×175 pixels up to 1000x1000 pixels.

Timing control is located in the CS7615 analog

processor, while the CS7666 synchronizes itself by

decoding the timing cues embedded in the CS7615

data stream. Alternately, the CS7666 accepts hori-

zontal and vertical timing signals on pin inputs.

The block diagram in Figure 1 illustrates a typical

system interconnect.

CS7615

CCD

CDS/ADC

6 512x480

Timing I2C

Vertical

Drive

6

+18V to +12V

CCD

Bias

CS7666

Image

Processor

I2C

2

+5V

CS4954

Video

Codec

I2C

Bus

Figure 1. Typical 4-Chip Digital CCD Camera

The CS7666 is a CCD camera color separation and

color-space processor designed to process the four-

color mosaic CCD imager data into ITU-601 com-

pliant 4:2:2 YCrCb digital component video. The

CS7666 timing control is based on the built-in crys-

tal oscillator or on the master clock provided by the

CS7615, and provides formatted component digital

video compliant with SMPTE-125 and ITU-656

transport protocols.

The CS7666 provides color separation of standard

MYCG chroma block data from industry standard

four-color CCD imagers. Gamma correction and

white balance adjustment functions are also includ-

ed in the CS7666. The YCrCb (luminance and

chrominace) data is output at the scaled CCD pixel

rate in 20-bit format, or at twice the scaled pixel

rate in 10-bit format (see discussion on Digital Out-

put Formats). The YCrCb output data from the

CS7666 conforms to the ITU-656 parallel compo-

nent digital video recommendation with embedded

synchronization (see Embedded EAV and SAV

discussion). External horizontal and vertical syn-

chronization signals are also provided to support

ITU-601 interfaces, as well as the PC-Card Zoom-

Video standard being used in notebook computers.

The CS7666 incorporates an internal horizontal

scaler which may be turned on to increase the hori-

zontal pixel count of the popular 360 (CIF) and 512

horizontal pixel per line imagers. The most com-

CCD

DATA

DEFORMATTER

COLOR SEPARATION

AND ANITALIASING

WHITE

BALANCE

AWB

CONTROL

GAMMA

CORRECTION

SCALER

OUTPUT

FORMATTER

YCrCb

DATA

SECONDARY

I2C BUS

I2C INTERFACE

REGISTER

BLOCK

PLL AND

CLOCK DRIVER

PRIMARY

I2C BUS

XTAL

Figure 2. CS7666 Block Diagram

OUTPUT

TIMING

VREF/VSYNC

HREF/HSYNC

6

DS302PP1

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