MXED101DI View Datasheet(PDF) - Clare Inc => IXYS
Part Name
Description
Manufacturer
MXED101DI Datasheet PDF : 14 Pages
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Digital Timing for Vcc in Range of 4.5 to 5.5 VDC
Parameter
Symbol
Min
Typ
Max
Shift Clock Frequency (VCC=4.5 + 5.5V)
fCLK
55
Shift Clock Frequency (VCC=3.0 to 4.4V)
40
Shift Clock Frequency Pulse Width
tSPW
7
22
(VCC=4.5 + 5.5V)
Shift Clock Frequency Pulse Width
tSPW
9.6
30
(VCC=3.0 to 4.4V)
Shift Clock Frequency Duty Cycle
DCSCK
40
50
60
Shift Clock to Latch Delay
tDSKL
3 (clock Cycles)
Exposure Clock Frequency
fEKF
10
Exposure Clock Pulse Width
tEPW
40
500
Exposure Duty Cycle
DCEX
40
50
60
Data Setup Time
tDSU
5
—
—
Data Hold Time
tDHD
5
—
—
Token Setup Time
tTSU
5
—
—
Token Hold Time
ttHD
5
—
—
Token Bit Output Delay
tSTD
—
—
13
Token Bit Pulse Width
tTPW
15
—
—
Latch Pulse Width
tLAPW
50
—
—
Last data to Latch Enable Time
tDLD
200
—
—
Latch Disable to Exposure Clock Time
tLED
50
—
—
Exposure Clock to Latch Enable Time
tDLE
50
—
—
Standby to Ready Time
tSTBY
10
MXED101
Units
MHz
MHz
nS
nS
%
nS
MHz
nS
%
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
mS
Output Channel Parameters
Parameter
Symbol
Typ
Min
Driver Output Voltage Compliance
VQn
Per bank max to min channel output
O<VQn<VDD - 3,
current ratio
IBANK
VQn match to 2V
1.0
High output die to low output die
average output current ratio
O<VQn<VDD - 3,
IDIE
VQn match to 2V
1.0
RRG match to 0.1%
Output Current Rise Time
tIOR
_
_
Output Current Fall Time
tIOF
_
_
Output Current Settling Time
tIOS
_
_
Exposure Clock to Output High Delay
tOHD
_
_
Exposure Clock to Output Low Delay
tOLD
_
_
Channel output current rise/fall time
tIORF
10% to 90%
Shorting Switch Resistance
V(Qn) = IV
Max
VDD-3
1.04
1.02
200
200
350
220
220
250
800
Units
Vdc
A/A
A/A
nS
nS
nS
nS
nS
nS
Ω
Rev. 9
www.clare.com
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