MXED101DI View Datasheet(PDF) - Clare Inc => IXYS
Part Name
Description
Manufacturer
MXED101DI Datasheet PDF : 14 Pages
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MXED101
Signal Definition
Name
I/0/A
VDD
VCC
GND
ISHRT
RSTB
I
CLKSH
I
LTKNB
I/O
RTKNB
I/O
DIRTKN
I
LE
I
DA(5-0)
I
DB(5-0)
I
DC(5-0)
I
CLKEX
I
TGR
I
GG
A
Description
Power supply for the 192 current driver output channels - 6 pads
Low voltage logic power supply - 2 pads
Ground - 4 pads
Ground used to short the 192 current driver output channels - 4 pads. Note: There can be high currents on this line.
It should be seperated from the circuit ground pads (GND) to prevent ground bounce.
Reset: Active low signal used to reset digital logic for test purposes. This input is pulled high internally.
Token Shift Clock: Used to shift tokens down the length of the driver IC. The direction of token shift is
determined by DIRTKN pin. It is possible to load only a portion of the 192 output channels prior to latching in
applications not requiring the full 192 channels. The speed of the clock is from DC to 55 MHz at 5V logic power
supply (40 MHz at 3.3V).
Left Token Bit: Used to pass the tokens into and out of the driver IC. The pin is used as input for shift right and as
output for shift left. High state represents the presence of token. The shifting is performed from DC to 55 MHz
(40 MHz at 3.3V).
Right Token Bit: Used to pass the tokens into and out of the driver IC. The pin is used as input for shift left and as
output for shift right. High state represents the presence of token. The shifting is performed from DC to 55 MHz
(40 MHz at 3.3V).
Token Direction: Used to determine the shift direction of the token. When the signal is high, causes the token to shift
left to right (1–>64) and when the signal is low causes the token to shift to left (64–>1). This input is pulled high
internally. The token shifts 3 cells at a time to account for the 3 parallel data inputs.
Latch Enable: Active high signal used to latch RGB data from the driver outputs into a set of transfer latches. Once a
line of data is latched into the transfer latch, OLED exposure can begin. At the same time, a new line of exposure data
can be loaded into the input register of the driver IC. On the rising edge of the of LE, all token registers are cleared, the
exposure counter is asynchronously preset to a low state and exposure data is allowed to pass from the input register
to the transfer latch. On the falling edge of LE, the exposure counter and output drivers are enabled within tLED (50 ns).
6-bit Data input A. Signal bus used for the exposure data input word for outputs 1,4,7,…,190. The driver performs
at clock speed from DC to 55 MHz (40 MHz at 3.3V).
6-bit Data input B. Signal bus used for the exposure data input word for outputs 2,5,8,…,191. The driver performs
at clock speed from DC to 55 MHz (40 MHz at 3.3V).
6-bit Data input C. Signal bus used for the exposure data input word for channels 3,6,9,…,192. The driver performs
at clock speed from DC to 55 MHz (40 MHz at 3.3V).
Exposure Clock: Signal (DC to 10 MHz signal) used to clock the input of the driver ICs exposure counter (6-bits).
The signal is used to cycle the driver IC internal counter from 0 up to 63. The signal must be cycled at least 64 times
between LE pulses to completely cycle the counter. The first rising edge of CLKEX will enable all non zero outputs with-
out changing the counter. Additional rising edges of CLKEX will increment the counter. When the counter and data of
values for an output match, the output is disabled until LE re-enables the exposure counter. Cycles of CLKEX beyond 64
will have no effect until the next cycle of LE re-enables the counter.
Binary/Grayscale: Signal used to determine if the driver IC is either 6 bit grayscale or binary. Low –> grayscale.
High –> Binary. This input is internally pulled to a logic low.
Global Gain: Used to set the global current gain. The voltage range on this pin is 0V to 12V when VDD is ≥ 15V. The
base current level is GG/RG, with a peak base current level of 1.455mA. This input is internally pulled to a logic low.
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