MXED101TP View Datasheet(PDF) - Clare Inc => IXYS

Part Name

Description

Manufacturer

MXED101TP

30V, 192-Channel OLED Display Driver

Clare Inc => IXYS 

MXED101

Functional Description

Output Current Hold-On-Time Control

There are two modes for controlling the 192 outputs current hold-on-times:

1- Grayscale: The grayscale is obtained when the TGR pin is low or open. Each of the three banks has a 6-bit con-

trol word, DA(5-0), DB(5-0), and DC(5-0), that is updated at the CLKSH signal clock which allows each output to

turn on for a period of 0 to 63 counts of the CLKEX signal clock.

2- Binary Mode: Binary mode is obtained when the TGR input signal is high. Data is loaded in a similar way that is

described in the grayscale mode. After the data is latched the DA5, DB5, or DC5 data bit is gated with CLKEX to

determine the on or off status of the output drivers.

Output Current Magnitude Control

GG, RG, GA(2-0), GB(2-0), and GC(2-0) controls the output current of the output drivers in the three banks. A pre-

cision 10.8 KΩ (+/- 0.1%) resistor is tied from RG to ground. A voltage between 0.5 and 12V is applied to GG to

adjust the overall brightness of the display. GA(2-0), GB(2-0), and GC(2-0) are 3-bit logic inputs that control the rel-

ative brightness of the A, B, and C banks output drivers respectively. The total output driver current is limited to a

maximum of 0.6 mA for each output. Below this limit, the individual output current for banks A, B, and C is pro-

grammed as follows:

I(out) = V(GG) x F(gain) = 5.79E-6 *V(GG)*F(gain)

10.8 Kohms

16

Where:

GA/GB/GC

(2-0)

0x7

0x6

0x5

0x4

F(gain)

31

26

22

19

GA/GB/GC

(2-0)

0x3

0x2

0x1

0x0

F(gain)

16

14

12

10

6

www.clare.com

Rev. 9

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