CXA2647N
• VC Buffer
• DVC Buffer
This outputs the VC ((1/2) VCC) voltage.
The maximum output current is approximately ±3mA.
Use this voltage as the analog block VC voltage.
VCC
This outputs the DVC ((1/2) DVCC) voltage.
The maximum output current is approximately ±3mA.
Use this voltage as the digital block VC voltage.
The each output DC voltage of FE, TE and CE is
level shifted using the DVC voltage as the reference.
40k
VC 27
25
40k
DVC 14
25
DVCC
40k
40k
• RFDC
The signals input to the A, B, C and D pins are added, amplified and the RFDC signal is output. ROM/RW
switching, low frequency gain adjustment and output DC voltage adjustment are possible.
A6
B7
C8
D9
ROM
VC
RW
VC
Control bias
30 VC – 1V to VC + 1V
ROM RW
24k
96k
5.1k
15k 10k
15k
ROM
15k
40k RW
15k
2.4k
3.3k
RFDCI 29
124
2k
VC
28 RFDC
124
RFDC = Gain (A + B + C + D)
Low frequency gain ROM: 16.5dB
RW: 28.5dB
Cut-off frequency fc (typ.)
ROM : 15MHz
RW : 6MHz
The gain can be adjusted by the external resistance connected between Pins 28 and 29.
The output voltage offset can be adjusted by controlling the Pin 30 voltage.
– 12 –