CXD2408AR View Datasheet(PDF) - Sony Semiconductor

Part Name

Description

Manufacturer

CXD2408AR

Timing Generator for Progressive Scan CCD Image Sensor

Sony Semiconductor 

CXD2408AR

5-1. Normal reset

In the normal reset mode, the reset signal is input for resetting, and the sync signal is output continuously from

that time. Only the mode which resets both HD and VD (HV reset) is supported.

When the H reset signal HRI is continuously with an H cycle, resetting is triggered at the first falling edge, and

after that point no resets are triggered at edges unless HD after resetting exceeds 2bits (163ns) on the internal

clock. In other words, the HRI input jitter is absorbed when it is up to 163 ns. The HRI minimum reset pulse

width is 0.3µs.

In the V direction, counting begins from VRI fall, and V is reset to cause VDO to fall after 262.5 – 3.5 = 259H.

The VRI minimum reset pulse width is 2H.

Resetting is done for ODD or EVEN field, depending on the input timing of the V reset signal. The identification

timing is shown in Electrical Characteristics (Field identification).

FIELD.E

FIELD.O

HRI

HDO

VRI

VDO

9H

259H

FIELD.O

FIELD.E

HRI

HDO

VRI

VDO

9H

259H

H reset

HRI

HD OUT

57.1 to 57.2µs (701 to 702 bit)

Reset

– 17 –

6.3 to 6.37µs

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