CY14B256L-SP35XC(2007) View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY14B256L-SP35XC Datasheet PDF : 17 Pages
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PRELIMINARY
CY14B256L
Pin Definitions
Pin Name IO Type
Description
A0 – A14
Input Address inputs used to select one of the 32,768 bytes of the nvSRAM.
DQ0 – DQ7 Input Output Bidirectional data IO lines. Used as input or output lines depending on operation.
NC
No Connect No Connects. This pin is not connected to the die.
WE
Input Write Enable Input, active LOW. When selected LOW, enables data on the IO pins to be written
to the address location latched by the falling edge of CE.
CE
Input Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input Output Enable, active LOW. The active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the IO pins to tri-state.
VSS
VCC
HSB
Ground Ground for the device. Must be connected to ground of the system.
Power Supply Power supply inputs to the device.
Input Output Hardware Store Busy. When low this output indicates a Hardware Store is in progress. When pulled
low external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up resistor
keeps this pin high if not connected. (connection optional)
VCAP Power Supply AutoStore capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
Device Operation
The CY14B256L nvSRAM is made up of two functional
components paired in the same physical cell. These are a
SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM can be transferred to the nonvolatile cell
(the STORE operation), or from the nonvolatile cell to SRAM
(the RECALL operation). This unique architecture allows all
cells to be stored and recalled in parallel. During the STORE
and RECALL operations SRAM READ and WRITE operations
are inhibited. The CY14B256L supports infinite reads and
writes just like a typical SRAM. In addition, it provides infinite
RECALL operations from the nonvolatile cells and up to
200,000 STORE operations.
SRAM READ
The CY14B256L performs a READ cycle whenever CE and
OE are low while WE and HSB are high. The address specified
on pins A0-14 determines which of the 32,768 data bytes will
be accessed. When the READ is initiated by an address
transition, the outputs will be valid after a delay of tAA (READ
cycle 1). If the READ is initiated by CE or OE, the outputs will
be valid at tACE or at tDOE, whichever is later (READ cycle 2).
The data outputs repeatedly responds to address changes
within the tAA access time without the need for transitions on
any control input pins, and remains valid until another address
change or until CE or OE is brought high, or WE or HSB is
brought low.
SRAM WRITE
A WRITE cycle is performed whenever CE and WE are low
and HSB is high. The address inputs must be stable before
entering the WRITE cycle and must remain stable until either
CE or WE goes high at the end of the cycle. The data on the
common IO pins IO0–7 will be written into the memory tSD
before the end of a WE controlled WRITE or before the end of
an CE controlled WRITE. Keep the OE HIGH during the entire
WRITE cycle to avoid data bus contention on common IO
lines.
If OE is left low, internal circuitry turns off the output buffers
tHZWE after WE goes low.
AutoStore Operation
The CY14B256L stores data to nvSRAM using one of three
storage operations. These three operations are Hardware
Store, activated by HSB, Software Store, activated by an
address sequence, and AutoStore, on device power down.
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B256L.
During normal operation, the device draws current from VCC
to charge a capacitor connected to the VCAP pin. This stored
charge will be used by the chip to perform a single STORE
operation. If the voltage on the VCC pin drops below VSWITCH,
the part automatically disconnects the VCAP pin from VCC. A
STORE operation will be initiated with power provided by the
VCAP capacitor.
Figure 1 on page 4 shows the proper connection of the storage
capacitor (VCAP) for automatic store operation. Refer to the DC
Electrical Characteristics on page 7 for the size of VCAP. The
voltage on the VCAP pin is driven to 5V by a charge pump
internal to the chip. A pull up must be placed on WE to hold it
inactive during power up.
To reduce unnecessary nonvolatile stores, AutoStore, and
Hardware Store operations will be ignored unless at least one
WRITE operation has taken place since the most recent
STORE or RECALL cycle. Software initiated STORE cycles
are performed regardless of whether a WRITE operation has
taken place. The HSB signal can be monitored by the system
to detect an AutoStore cycle is in progress.
Document #: 001-06422 Rev. *E
Page 3 of 17
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