CY22180SXI-XXX View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

CY22180SXI-XXX

Very Low Jitter Field and Factory Programmable Clock Generator

Cypress Semiconductor 

PRELIMINARY

CY22180

l

DC Electrical Characteristics

Parameter

Description

Condition

IOH

Output High Current

VOH = VDD – 0.5V, VDD = 3.3V (source)

IOL

Output Low Current

VOL = 0.5V, VDD = 3.3V (sink)

VIH

Input High Voltage

CMOS levels, 70% of VDD

VIL

Input Low Voltage

CMOS levels, 30% of VDD

IIH

Input High Current, PD#/OE VIN= VDD

IIL

Input Low Current, PD#/OE VIN = VSS, pull up disabled

VIN = VSS, pull up enabled

IOZ

Output Leakage Current Three-state output, PD#/OE = 0

CXIN or CXOUT[1] Programmable Capacitance Capacitance at minimum setting

at pin 1 and pin 8

Capacitance at maximum setting

CIN[1]

Input Capacitance at

PD#/OE

IDD

IDDS

Supply Current

Standby current

fIN = 10 MHz, fOUT = 33 MHz, REFOUT off

Device powered down with PD# = 0V (driven

reference pulled down)

Min Typ Max Unit

10 12

mA

10 12

mA

0.7VDD – VDD + 0.3 V

–0.3 – 0.3VDD V

–

–

10 μA

–

–

10 μA

–

–

55 μA

–10

10 μA

–

12

–

pF

–

60

–

pF

–

5

7

pF

–

11

15 mA

–

10

40 μA

AC Electrical Characteristics[1]

Parameter

Description

Condition

Min Typ Max Unit

DC

Output Duty Cycle

CLKOUT < 125 MHz, Measured at VDD/2

45 50

55

%

Output Duty Cycle

CLKOUT > 125 MHz, Measured at VDD/2

40 50

60

%

Output Duty Cycle

REFOUT, Measured at VDD/2

Duty Cycle of CLKIN = 50%

45 50

55

%

SR1

SR2

TPJ1[2, 3]

TPJ2[2, 3]

Rising Edge Slew Rate

Falling Edge Slew Rate

CLKOUT pk-pk Period

Jitter, REFOUT off

CLKOUT from 20 to 200 MHz;

2

REFOUT from 10 to 133 MHz. 20%–80% of VDD

CLKOUT from 20 to 200 MHz;

2

REFOUT from 10 to 133 MHz. 80%–20% of VDD

CLKOUT = 20–200 MHz

–

CLKOUT pk-pk Period

CLKIN = 10 MHz, CLKOUT = 20, 33, 66, 80,

–

Jitter, REFOUT off, specific 106.25, 125, 133, or 200 MHz

frequencies

CLKIN = 25 MHz, CLKOUT = 125 MHz

–

3

– V/ns

3

– V/ns

–

75 ps

(±38)

–

60 ps

(±30)

–

56 ps

(±28)

CLKIN = 30 MHz, CLKOUT = 33, 66, 80, 106.25, –

125, or 133 MHz

–

62 ps

(±31)

CLKIN = 66 MHz, CLKOUT = 33 or 66 MHz

–

–

47 ps

(±24)

CLKIN = 66 MHz, CLKOUT = 80, 106.25, 125,

–

–

68 ps

133, 166, or 200 MHz

(±34)

CLKIN = 133 MHz, CLKOUT = 33, 66, or 80 MHz –

–

68 ps

(±34)

CLKIN = 133 MHz,

CLKOUT = 125, 133, or 166 MHz

–

–

52 ps

(±26)

Notes

1. Guaranteed by characterization, not 100% tested.

2. Jitter is configuration dependent. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, temperature, and output

load. For more information, refer to the application note, “Jitter in PLL Based Systems: Causes, Effects, and Solutions”.

3. Cycle-to-Cycle Jitter (peak) is always less than Period Jitter (peak-to-peak). Peak-to-Peak Period Jitter is the difference between the shortest and longest

measured periods.

Document #: 001-15577 Rev. **

Page 4 of 8

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