CY22388/89/91
Test and Measurement Set-up
Figure 3. Test and Measurement
VDDs
0 .1 F
DUT
Outputs
C LO AD
Voltage and Timing Definitions
GND
Figure 4. Duty Cycle Definition
t1
t2
Clock
Output
VDD
50% of VDD
0V
Figure 5. ER = (0.6 VDD)/t3, EF = (0.6 VDD)/t4
t3
t4
VDD
80% of VDD
Clock
Output
20% of VDD
0V
Figure 6. FS Controlled Clock Output
Finish Cycle
Start at Full Cycle
FS
TWAIT
Document #: 38-07734 Rev. *B
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