CY62136CV33LL-70BAI View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY62136CV33LL-70BAI Datasheet PDF : 13 Pages
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CY62136CV30/33 MoBL
CY62136CV MoBL
Switching Characteristics Over the Operating Range[8]
Parameter
Read Cycle
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
tDBE
tLZBE
tHZBE
Write Cycle[11]
tWC
tSCE
tAW
tHA
tSA
tPWE
tBW
tSD
tHD
tHZWE
tLZWE
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[9]
OE HIGH to High-Z[9, 10]
CE LOW to Low-Z[9]
CE HIGH to High-Z[9, 10]
CE LOW to Power-up
CE HIGH to Power-down
BHE/BLE LOW to Data Valid
BHE/BLE LOW to Low-Z[9]
BHE/BLE HIGH to High-Z[9, 10]
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BHE/BLE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z[9, 10]
WE HIGH to Low-Z[9]
55 ns
Min.
Max.
55
55
10
55
25
5
20
10
20
0
55
25
5
20
55
45
45
0
0
40
50
25
0
20
10
70 ns
Min.
Max.
Unit
70
ns
70
ns
10
ns
70
ns
35
ns
5
ns
25
ns
10
ns
25
ns
0
ns
70
ns
35
ns
5
ns
25
ns
70
ns
60
ns
60
ns
0
ns
0
ns
45
ns
60
ns
30
ns
0
ns
25
ns
10
ns
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[12, 13]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
10. ItHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
11. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
12. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL.
13. WE is HIGH for read cycle.
Document #: 38-05199 Rev. *D
Page 5 of 13
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