CY7B9940V View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7B9940V Datasheet PDF : 11 Pages
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Pin Definitions
RoboClockII™ Junior,
CY7B9930V, CY7B9940V
44-Pin TQFP
GND
2QB1
VCCN
2QB0
GND
GND
2QA1
VCCN
2QA0
GND
GND
44 43 42 41 40 39 38 37 36 35 34
1
2
3
4
5
6
7
8
9
10
11
12
CY7B9930V/40V
13 14 15 16 17 18 19 20
33
32
31
30
29
28
27
26
25
24
23
21 22
VCCQ
REFA+
REFA –
REFSEL
REFB–
REFB+
FS
GND
VCCQ
DIS2
DIS1
Name
FBKA
REFA+, REFA–
REFB+, REFB–
I/O
Input
Input
REFSEL
Input
FS[3]
FBDS[0:1][3]
DIS[1:2]
Input
Input
Input
LOCK
Output
Output_Mode[3] Input
QFA[0:1]
Output
[1:2]Q[A:B][0:1]
VCCN
VCCQ
GND
Output
Type
LVTTL
LVTTL/
LVDIFF
LVTTL
3 Level
Input
3 Level
Input
LVTTL
LVTTL
3 Level
Input
LVTTL
LVTTL
PWR
PWR
PWR
Description
Feedback Input.
Reference Inputs: These inputs operate as either differential PECL or single ended TTL
reference inputs to the PLL. When operating as a single ended LVTTL input, leave the
complementary input must be left open.
Reference Select Input: The REFSEL input controls reference input configuration. When
LOW, it uses the REFA pair as the reference input. When HIGH, it uses the REFB pair as
the reference input. This input has an internal pull down.
Frequency Select: Set this input according to the nominal frequency (fNOM). See Table 1.
Feedback Divider Function Select. These inputs determine the function of the QFA0 and
QFA1 outputs. See Table 2.
Output Disable: Each input controls the state of the respective output bank. When HIGH,
the output bank is disabled to the “HOLD OFF” or “HI-Z” state; the disable state is deter-
mined by OUTPUT_MODE. When LOW, the [1:4]Q[A:B][0:1] is enabled. See Table 3.
These inputs each have an internal pull down.
PLL Lock Indicator: When HIGH, this output indicates that the internal PLL is locked to
the reference signal. When LOW, the PLL is attempting to acquire lock.
Output Mode: This pin determines the clock outputs’ disable state. When this input is HIGH,
the clock outputs disable to high impedance (HI-Z). When this input is LOW, the clock
outputs disables to “HOLD OFF” mode. When in MID, the device enters factory test mode.
Clock Feedback Output: This pair of clock outputs connects to the FB input. These outputs
have numerous divide options. The function is determined by the setting of the FBDS[0:1]
pins.
Clock Output.
Output Buffer Power: Power supply for each output pair.
Internal Power: Power supply for the internal circuitry.
Device Ground.
Note
3. For all tri-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry
holds an unconnected input to VCC/2.
Document Number: 38-07271 Rev. *C
Page 4 of 11
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