CY7B9930V View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7B9930V Datasheet PDF : 11 Pages
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RoboClockII™ Junior,
CY7B9930V, CY7B9940V
Electrical Characteristics Over the Operating Range (continued)
Parameter
Description
Operating Current
ICCI
Internal operating
current
ICCN
Output current
dissipation/pair[6]
CY7B9930V
CY7B9940V
CY7B9930V
CY7B9940V
Test Conditions
VCC = Max., fMAX[5]
VCC = Max.,
CLOAD = 25 pF,
RLOAD = 50Ω at VCC/2,
fMAX
Min.
–
–
–
–
Max.
200
200
40
50
Unit
mA
mA
mA
mA
Capacitance
Parameter
Description
CIN
Input capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 3.3V
Min.
Max.
Unit
–
5
pF
Switching Characteristics
Over the Operating Range[7, 8, 9, 10, 11]
Parameter
Description
CY7B9930/40V-2 CY7B9930/40V-5
Unit
Min. Max. Min. Max.
fin
Clock input frequency
CY7B9930V 12
100
12
100
MHz
CY7B9940V 24
200
24
200
MHz
fout
Clock input frequency
CY7B9930V 12
100
12
100
MHz
CY7B9940V 24
200
24
200
MHz
tSKEWPR
tSKEWBNK
Matched pair skew[12, 13]
Intrabank skew[12, 13]
–
185
–
185
ps
–
200
–
250
ps
tSKEW0
Output-Output skew (same frequency and phase, rise to rise, fall –
to fall)[12, 13]
250
–
550
ps
tSKEW1
Output-Output skew (same frequency and phase, other banks at –
different frequency, rise to rise, fall to fall)[12, 13]
250
–
650
ps
tCCJ1-3
Cycle-to-cycle jitter (divide by 1 output frequency,
FB = divide by 1, 2, 3)
–
150
–
150 ps Peak-
Peak
tCCJ4-12
Cycle-to-cycle jitter (divide by 1 output frequency,
FB = divide by 4, 5, 6, 8, 10, 12)
–
100
–
100 ps Peak-
Peak
tPD
tPDDELTA
tREFpwh
tREFpwl
tr/tf
Propagation delay, REF to FB Rise
Propagation delay difference between two devices[14]
REF input (pulse width HIGH)[15]
REF input (pulse width LOW)[15]
Output rise/fall time[16]
–250 250 –500 500
ps
–
200
200
ps
2.0
–
2.0
–
ns
2.0
–
2.0
–
ns
0.15
2.0
0.15
2.0
ns
Notes
5. ICCI measurement is performed with Bank1 and FB Bank configured to run at maximum frequency (fNOM = 100 MHz for CY7B9930V, fNOM = 200 MHz for CY7B9940V),
and all other clock output banks to run at half the maximum frequency. FS and OUTPUT_MODE are asserted to the HIGH state.
6. This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum ICCN at maximum frequency and maximum load of
25 pF terminated to 50Ω at VCC/2.
7. This is for non-three level inputs.
8. Assumes 25 pF Max. Load Capacitance up to 185 Mhz. At 200 MHz the max load is 10 pF.
9. Both outputs of pair must be terminated, even if only one is being used.
10. Each package must be properly decoupled.
11. AC parameters are measured at 1.5V, unless otherwise indicated.
12. Test Load CL= 25 pF, terminated to VCC/2 with 50Ω.
13. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when all outputs
are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF.
14. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
15. Tested initially and after any design or process changes that may affect these parameters.
16. Rise and fall times are measured between 2.0V and 0.8V.
Document Number: 38-07271 Rev. *C
Page 6 of 11
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