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CY7C017AV View Datasheet(PDF) - Cypress Semiconductor

Part Name
Description
Manufacturer
CY7C017AV
Cypress
Cypress Semiconductor Cypress
CY7C017AV Datasheet PDF : 20 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Switching Characteristics Over the Operating Range[15] (continued)
Parameter
Description
tHD
Data Hold From Write End
tHZWE[18, 19]
R/W LOW to High Z
tLZWE[18, 19]
R/W HIGH to Low Z
tWDD[20]
Write Pulse to Data Delay
tDDD[20]
Write Data Valid to Read Data Valid
BUSY TIMING[21]
tBLA
BUSY LOW from Address Match
tBHA
BUSY HIGH from Address Mismatch
tBLC
BUSY LOW from CE LOW
tBHC
BUSY HIGH from CE HIGH
tPS
Port Set-Up for Priority
tWB
R/W HIGH after BUSY (Slave)
tWH
R/W HIGH after BUSY HIGH (Slave)
tBDD[22]
BUSY HIGH to Data Valid
INTERRUPT TIMING[21]
tINS
INT Set Time
tINR
INT Reset Time
SEMAPHORE TIMING
tSOP
tSWRD
tSPS
tSAA
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
-20
-25
Min. Max. Min. Max.
Unit
0
0
ns
12
15
ns
3
3
ns
40
50
ns
30
35
ns
20
20
ns
20
20
ns
20
20
ns
16
17
ns
5
5
ns
0
0
ns
15
17
ns
20
25
ns
20
20
ns
20
20
ns
10
12
ns
5
5
ns
5
5
ns
20
25
ns
Data Retention Mode
The
CY7C0138AV/144AV/006AV/007AV
and
CY7C139AV/145AV/016AV/017AV are designed with battery
backup in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules ensure data
retention:
1. Chip enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2V.
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (3.0 volts).
Timing
VCC
CE
Data Retention Mode
3.0V
VCC > 2.0V
3.0V
VCC to VCC – 0.2V
tRC
VIH
Parameter
ICCDR1
Test Conditions[23]
@ VCCDR = 2V
Max.
50
Unit
µA
Notes:
20. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
21. Test conditions used are Load 2.
22. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
23. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
Document #: 38-06051 Rev. *C
Page 9 of 20

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