CY7C1002-25VC View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1002-25VC Datasheet PDF : 9 Pages
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CY7C1001
PRELIMINARY CY7C1002
AC Test Loads and Waveforms
W R1 480
5V
5V
W R1 480
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
OUTPUT
W R2
255
5 pF
INCLUDING
JIG AND
SCOPE
(b)
W R2
255
C1001-3
3.0V
GND
< 3 ns
Equivalent to:
OUTPUT
THÉVENIN EQUIVALENT
W 167
1.73V
ALL INPUT PULSES
90%
10%
90%
10%
< 3 ns
C1001-4
Switching Characteristics Over the Operating Range[3, 6]
Parameter
Description
7C1001-12
7C1002-12
Min. Max.
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
tLZCE
tHZCE
CE LOW to Data Valid
CE LOW to Low Z[7]
CE HIGH to High Z[7, 8]
tPU
CE LOW to PowerĆUp
tPD
CE HIGH to PowerĆDown
WRITE CYCLE[9]
12
12
3
12
3
6
0
12
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
tDWE
tDCE
tADV
Write Cycle Time
CE LOW to Write End
Address SetĆUp to Write End
Address Hold from Write End
Address SetĆUp to Write Start
WE Pulse Width
Data SetĆUp to Write End
Data Hold from Write End
WE HIGH to Low Z[7]
WE LOW to High Z[7, 8]
WE LOW to Data Valid (7C1001)
CE LOW to Data Valid (7C1001)
Data Valid to Output Valid (7C1001)
12
10
10
0
0
10
7
0
3
6
12
12
12
7C1001-15
7C1002-15
Min. Max.
15
15
3
15
3
7
0
15
15
12
12
0
0
12
8
0
3
7
15
15
15
7C1001-20
7C1002-20
Min. Max.
20
20
3
20
3
8
0
20
20
15
15
0
0
15
10
0
3
8
20
20
20
7C1001-25
7C1002-25
Min. Max.
25
25
3
25
3
10
0
25
25
20
20
0
0
20
15
0
3
10
25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
6. Test conditions assume signal transition time of 3 ns or less, timing refĆ
erence levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOL/IOH and 30ĆpF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than
tLZCE and tHZWE is less than tLZWE for any given device.
8. tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in
part (b) of AC Test Loads. Transition is measured ±500 mV from
steadyĆstate voltage.
9. The internal write time of the memory is defined by the overlap of CE
and WE LOW. CE and WE must be LOW to initiate a write, and the
transition of any of these signals can terminate the write. The input
data setĆup and hold timing should be referenced to the leading edge
of the signal that terminates the write.
3
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