CY7C107-20VC View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C107-20VC Datasheet PDF : 8 Pages
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CY7C107
CY7C1007
AC Test Loads and Waveforms
5V
OUTPUT
R1 480Ω
5V
OUTPUT
R1 480Ω
30 pF
INCLUDING
JIG AND
SCOPE (a)
R2
255Ω
5 pF
INCLUDING
JIG AND
SCOPE (b)
R2
255Ω
107-3
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
167Ω
1.73V
3.0V
GND
10%
≤ 3 ns
ALL INPUT PULSES
90%
90%
10%
≤ 3 ns
107-4
Switching Characteristics[5] Over the Operating Range
7C107-12 7C107-15 7C107-20 7C107-25
7C1007-12 7C1007-15 7C1007-20 7C1007-25
7C107-35
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
12
15
20
25
35
ns
tAA
Address to Data Valid
12
15
20
25
35 ns
tOHA
Data Hold from Address
3
3
3
3
3
ns
Change
tACE
tLZCE
tHZCE
CE LOW to Data Valid
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
12
15
20
25
35 ns
3
3
3
3
3
ns
6
7
8
10
10 ns
tPU
CE LOW to Power-Up
0
0
0
0
0
ns
tPD
CE HIGH to Power-Down
12
15
20
25
35 ns
WRITE CYCLE[8]
tWC
Write Cycle Time
12
15
20
25
35
ns
tSCE
CE LOW to Write End
10
12
15
20
25
ns
tAW
Address Set-Up to Write
10
12
15
20
25
ns
End
tHA
Address Hold from Write
0
0
0
0
0
ns
End
tSA
Address Set-Up to Write
0
0
0
0
0
ns
Start
tPWE
WE Pulse Width
10
12
15
20
25
ns
tSD
Data Set-Up to Write End 7
8
10
15
20
ns
tHD
tLZWE
tHZWE
Data Hold from Write End 0
0
0
0
0
ns
WE HIGH to Low Z[6]
3
3
3
3
3
ns
WE LOW to High Z[6, 7]
6
7
8
10
10 ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device.
7. tHZCE and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
4
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