CY7C1007D(2007) View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1007D Datasheet PDF : 10 Pages
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Switching Characteristics (Over the Operating Range) [6]
Parameter
Description
Read Cycle
tpower [7]
VCC(typical) to the first access
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tLZCE
CE LOW to Low Z [8]
tHZCE
CE HIGH to High Z [8, 9]
tPU [10]
CE LOW to Power-Up
tPD [10]
CE HIGH to Power-Down
Write Cycle [11]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z [8]
WE LOW to High Z [8, 9]
CY7C107D
CY7C1007D
7C107D-10
7C1007D-10
Unit
Min
Max
100
µs
10
ns
10
ns
3
ns
10
ns
3
ns
5
ns
0
ns
10
ns
10
ns
7
ns
7
ns
0
ns
0
ns
7
ns
6
ns
0
ns
3
ns
6
ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device.
9. tHZCE and tHZWE are specified with a load capacitance of 5 pF as in part (c) of “AC Test Loads and Waveforms [5]” on page 4. Transition is measured when the outputs enter a
high impedance state.
10. This parameter is guaranteed by design and is not tested.
11. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Document #: 38-05469 Rev. *E
Page 5 of 10
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