CY7C1032-8 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1032-8 Datasheet PDF : 12 Pages
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CY7C1031
CY7C1032
64K x 18 Synchronous
Cache RAM
Features
• Supports 66-MHz Pentium® microprocessor cache sys-
tems with zero wait states
• 64K by 18 common I/O
• Fast clock-to-output times
— 8.5 ns
• Two-bit wraparound counter supporting Pentium mi-
croprocessor and 486 burst sequence (7C1031)
• Two-bit wraparound counter supporting linear burst se-
quence (7C1032)
• Separate processor and controller address strobes
• Synchronous self-timed write
• Direct interface with the processor and external cache
controller
• Asynchronous output enable
• I/Os capable of 3.3V operation
• JEDEC-standard pinout
• 52-pin PLCC packaging
Functional Description
The CY7C1031 and CY7C1032 are 64K by 18 synchronous
cache RAMs designed to interface with high-speed micropro-
cessors with minimum glue logic. Maximum access delay from
clock rise is 8.5 ns. A 2-bit on-chip counter captures the first
address in a burst and increments the address automatically
for the rest of the burst access.
The CY7C1031 is designed for Intel® Pentium and i486 CPU-
based systems; its counter follows the burst sequence of the
Pentium and the i486 processors. The CY7C1032 is architect-
ed for processors with linear burst sequences. Burst accesses
can be initiated with the processor address strobe (ADSP) or
the cache controller address strobe (ADSC) inputs. Address
advancement is controlled by the address advancement (ADV)
input.
A synchronous self-timed write mechanism is provided to sim-
plify the write interface. A synchronous chip select input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.
Logic Block Diagram
Pin Configuration
18
PLCC
Top View
A15 –A0
ADV
16 14
ADDR
REG 14
2
2
ADV
LOGIC
DATA IN
REGISTER
9
9
16
64K X 9
64K X 9
RAM ARRAY RAM ARRAY
CLK
ADSP
ADSC
CS
WH
WL
WH
TIMING
WL
CONTROL
9
9
DQ8
DQ9
VCCQ
VSSQ
DQ10
DQ11
DQ12
DQ13
VSSQ
VCCQ
DQ14
DQ15
DP1[1]
7 6 5 4 3 2 1 52 51 50 49 48 47
8
46
9
45
10
44
11
43
12
42
13
7C1031
41
14
7C1032
40
15
39
16
38
17
37
18
36
19
35
20
34
2122 23 24 25 26 27 28 29 30 31 32 33
[1]
DP0
DQ7
DQ6
VCCQ
VSSQ
DQ5
DQ4
DQ3
DQ2
VSSQ
VCCQ
DQ1
DQ0
18
OE
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Commercial
Intel and Pentium are trademarks of Intel Corporation.
Note:
1. DP0 and DP1 are functionally equivalent to DQx.
1031–2
DQ15 – DQ0
DP1– DP0
7C1031–8
7C1032–8
8.5
280
7C1031–10
7C1032–10
10
280
1031–1
7C1031–12
7C1032–12
12
230
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
November 30, 1999
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