CY7C1032-8 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1032-8 Datasheet PDF : 12 Pages
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CY7C1031
CY7C1032
Functional Description (continued)
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) CS is LOW and (2) ADSP is LOW.
ADSP-triggered write cycles are completed in two clock peri-
ods. The address at A0 through A15 is loaded into the address
register and address advancement logic and delivered to the
RAM core. The write signal is ignored in this cycle because the
cache tag or other external logic uses this clock period to per-
form address comparisons or protection checks. If the write is
allowed to proceed, the write input to the CY7C1031 and
CY7C1032 will be pulled LOW before the next clock rise.
ADSP is ignored if CS is HIGH.
If WH, WL, or both are LOW at the next clock rise, information
presented at DQ0–DQ15 and DP0–DP1 will be written into the
location specified by the address advancement logic. WL con-
trols the writing of DQ0–DQ7 and DP0 while WH controls the
writing of DQ8–DQ15 and DP1. Because the CY7C1031 and
CY7C1032 are common-I/O devices, the output enable signal
(OE) must be deasserted before data from the CPU is deliv-
ered to DQ0–DQ15 and DP0–DP1. As a safety precaution, the
appropriate data lines are three-stated in the cycle where WH,
WL, or both are sampled LOW, regardless of the state of the
OE input.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at rising edge of the clock: (1) CS is LOW, (2) ADSC
is LOW, and (3) WH or WL are LOW. ADSC-triggered access-
es are completed in a single clock cycle.
The address at A0 through A15 is loaded into the address reg-
ister and address advancement logic and delivered to the RAM
core. Information presented at DQ0–DQ15 and DP0–DP1 will
be written into the location specified by the address advance-
ment logic. Since the CY7C1031 and the CY7C1032 are com-
mon-I/O devices, the output enable signal (OE) must be deas-
serted before data from the cache controller is delivered to the
data and parity lines. As a safety precaution, the appropriate
data and parity lines are three-stated in the cycle where WH
and WL are sampled LOW regardless of the state of the OE
input.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CS is LOW, (2) ADSP or ADSC
is LOW, and (3) WH and WL are HIGH. The address at A0
through A15 is stored into the address advancement logic and
delivered to the RAM core. If the output enable (OE) signal is
asserted (LOW), data will be available at the data outputs a
maximum of 8.5 ns after clock rise. ADSP is ignored if CS is
HIGH.
Burst Sequences
The CY7C1031 provides a 2-bit wraparound counter, fed by
pins A0–A1, that implements the Intel 80486 and Pentium pro-
cessor’s address burst sequence (see Table 1). Note that the
burst sequence depends on the first burst address.
Table 1. Counter Implementation for the Intel
Pentium/80486 Processor’s Sequence
First
Address
AX + 1, Ax
00
01
10
11
Second
Address
AX + 1, Ax
01
00
11
10
Third
Address
AX + 1, Ax
10
11
00
01
Fourth
Address
AX + 1, Ax
11
10
01
00
The CY7C1032 provides a two-bit wraparound counter, fed by
pins A0–A1, that implements a linear address burst sequence (see
Table 2).
Table 2. Counter Implementation for a Linear Sequence
First
Address
AX + 1, Ax
00
01
10
11
Second
Address
AX + 1, Ax
01
10
11
00
Third
Address
AX + 1, Ax
10
11
00
01
Fourth
Address
AX + 1, Ax
11
00
01
10
Application Example
Figure 1 shows a 512-Kbyte secondary cache for the Pentium
microprocessor using four CY7C1031 cache RAMs.
2
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