CY7C1069AV33 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1069AV33 Datasheet PDF : 9 Pages
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AC Switching Characteristics Over the Operating Range [7]
Parameter
Read Cycle
tpower
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
Write Cycle[10, 11]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
Description
VCC(typical) to the First Access[8]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE1 LOW/CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[9]
OE HIGH to High-Z[9]
CE1 LOW/CE2 HIGH to Low-Z[9]
CE1 HIGH/CE2 LOW to High-Z[9]
CE1 LOW/CE2 HIGH to Power-up[10]
CE1 HIGH/CE2 LOW to Power-down[10]
Write Cycle Time
CE1 LOW/CE2 HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z[9]
WE LOW to High-Z[9]
Data Retention Waveform
–10
Min.
Max.
1
10
10
3
10
5
1
5
3
5
0
10
10
7
7
0
0
7
5.5
0
3
5
DATA RETENTION MODE
VCC
3.0V
VDR > 2V
tCDR
CE
CY7C1069AV33
–12
Min.
Max.
Unit
1
ms
12
ns
12
ns
3
ns
12
ns
6
ns
1
ns
6
ns
3
ns
6
ns
0
ns
12
ns
12
ns
8
ns
8
ns
0
ns
0
ns
8
ns
6
ns
0
ns
3
ns
6
ns
3.0V
tR
Notes:
6. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the
minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.
8. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a Read/Write operation is
started.
9. tHZOE, tHZSCE, tHZWE and tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from
steady-state voltage.
10. These parameters are guaranteed by design and are not tested.
11. The internal Write time of the memory is defined by the overlap of CE1 LOW/CE2 HIGH, and WE LOW. CE1 and WE must be LOW along with CE2 HIGH to initiate
a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the
signal that terminates the Write.
12. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05255 Rev. *F
Page 4 of 9
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