CY7C107BN View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C107BN Datasheet PDF : 7 Pages
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AC Test Loads and Waveforms
5V
OUTPUT
R1 480Ω
5V
OUTPUT
R1 480Ω
30 pF
INCLUDING
JIG AND
SCOPE (a)
R2
255Ω
5 pF
INCLUDING
JIG AND
SCOPE (b)
R2
255Ω
CY7C107BN
CY7C1007BN
3.0V
GND
10%
≤ 3 ns
ALL INPUT PULSES
90%
90%
10%
≤ 3 ns
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
167Ω
1.73V
Switching Characteristics[5] Over the Operating Range
7C107BN-15
7C1007BN-15
Parameter
Description
Min.
Max.
Unit
READ CYCLE
tRC
tAA
tOHA
tACE
tLZCE
tHZCE
tPU
tPD
WRITE CYCLE[8]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
15
ns
15
ns
3
ns
15
ns
3
ns
7
ns
0
ns
15
ns
tWC
Write Cycle Time
15
ns
tSCE
CE LOW to Write End
12
ns
tAW
Address Set-Up to Write End
12
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-Up to Write Start
0
ns
tPWE
WE Pulse Width
12
ns
tSD
Data Set-Up to Write End
8
ns
tHD
tLZWE
tHZWE
Data Hold from Write End
WE HIGH to Low Z[6]
WE LOW to High Z[6, 7]
0
ns
3
ns
7
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device.
7. tHZCE and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any
of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Document #: 001-06426 Rev. **
Page 3 of 7
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