CY7C1009D View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

CY7C1009D

1-Mbit (128K x 8) Static RAM

Cypress Semiconductor 

CY7C109D

CY7C1009D

Data Retention Characteristics (Over the Operating Range)

Parameter

Description

Conditions

VDR

ICCDR

tCDR [4]

tR [13]

VCC for Data Retention

Data Retention Current

VCC = VDR = 2.0V,

CE1 > VCC – 0.3V or CE2 < 0.3V,

VIN > VCC – 0.3V or VIN < 0.3V

Chip Deselect to Data Retention Time

Operation Recovery Time

Data Retention Waveform

DATA RETENTION MODE

VCC

4.5V

VDR > 2V

tCDR

CE

Min Max Unit

2.0

V

3

mA

0

ns

tRC

ns

4.5V

tR

Switching Waveforms

Read Cycle No. 1 (Address Transition Controlled) [14, 15]

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

Read Cycle No. 2 (OE Controlled) [15, 16]

ADDRESS

CE1

CE2

OE

DATA OUT

VCC

SUPPLY

CURRENT

tRC

tACE

tDOE

tLZOE

HIGH IMPEDANCE

tLZCE

tPU

50%

DATA VALID

Notes

13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 µs or stable at VCC(min) > 50 µs.

14. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.

15. WE is HIGH for read cycle.

16. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.

Document #: 38-05468 Rev. *E

DATA VALID

tHZOE

tHZCE

HIGH

IMPEDANCE

tPD

ICC

50%

ISB

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