CY7C1217F-100AC View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

CY7C1217F-100AC

1-Mbit (32K x 36) Flow-Through Sync SRAM

Cypress Semiconductor 

Timing Diagrams (continued)

Read/Write Timing[16, 18, 19]

tCYC

CLK

ADSP

t

CH

tCL

tADS tADH

ADSC

ADDRESS A1

tAS tAH

A2

BWE, BW[A:D]

CE

tCES tCEH

A3

A4

t

WES

tWEH

CY7C1217F

A5

A6

ADV

OE

Data In (D)

Data Out (Q)

High-Z

t

OEHZ

Q(A1)

Q(A2)

Back-to-Back READs

tDS tDH

D(A3)

Single WRITE

tOELZ

tCDV

Q(A4)

Q(A4+1) Q(A4+2) Q(A4+3)

BURST READ

DON’T CARE

UNDEFINED

Notes:

18. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.

19. GW is HIGH.

D(A5)

D(A6)

Back-to-Back

WRITEs

Document #: 38-05430 Rev. *A

Page 11 of 14

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