CY7C1217F-100AC View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1217F-100AC Datasheet PDF : 14 Pages
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CY7C1217F
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
00
01
10
01
00
11
10
11
00
11
10
01
Fourth
Address
A1, A0
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
10
11
00
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to snooze current
ZZ Inactive to exit snooze current
Test Conditions
Min.
Max.
Unit
ZZ > VDD – 0.2V
40
mA
ZZ > VDD – 0.2V
2tCYC
ns
ZZ < 0.2V
2tCYC
ns
This parameter is sampled
2tCYC
ns
This parameter is sampled
0
ns
Truth Table [2, 3, 4, 5, 6]
Cycle Description
Deselected Cycle,
Power-down
Address
Used
None
CE1 CE3 CE2 ZZ ADSP ADSC ADV
H X XL X
L
X
WRITE
X
OE CLK DQ
X L-H Three-State
Deselected Cycle,
Power-down
None
L X LL L
X
X
X
X L-H Three-State
Deselected Cycle,
Power-down
None
L H XL L
X
X
X
X L-H Three-State
Deselected Cycle,
Power-down
None
L X LL H
L
X
X
X L-H Three-State
Deselected Cycle,
Power-down
None
X X XL H
L
X
X
X L-H Three-State
Snooze Mode, Power-down None
X X XH X
X
X
X
X X Three-State
Read Cycle, Begin Burst
External L L H L L
X
X
X
L L-H Q
Read Cycle, Begin Burst
External L L H L L
X
X
X
H L-H Three-State
Write Cycle, Begin Burst
External L L H L H
L
X
L
X L-H D
Read Cycle, Begin Burst
External L L H L H
L
X
H
L L-H Q
Read Cycle, Begin Burst
External L L H L H
L
X
H
H L-H Three-State
Read Cycle, Continue Burst Next
X X XL H
H
L
H
L L-H Q
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW= L. WRITE = H when all Byte Write Enable signals
(BWA, BWB, BWC, BWD), BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: D]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the Write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Three-State when
OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05430 Rev. *A
Page 5 of 14
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