XC68EZ328ZC16V View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
Manufacturer
XC68EZ328ZC16V Datasheet PDF : 246 Pages
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Basic Architecture
PARALLEL I/O PORTS
SYSTEM INTEGRATION MODULE
8-/16-BIT
68000 BUS
INTERFACE
ENHANCED
REAL-TIME
CLOCK
IN-CIRCUIT
EMULATION
INTERRUPT
CONTROLLER
DRAM
CONTROLLER
BOOTSTRAP
MODE
PHASE-LOCKED
LOOP AND
POWER CONTROL
68EC000 HCMOS
STATIC
CORE
68EC000 INTERNAL BUS
LCD
CONTROLLER
SPI
PWM
16-BIT
TIMER
MODULE
UART
WITH
INFRA-RED
SUPPORT
PARALLEL I/O PORTS
Figure 1-1. MC68EZ328 Block Diagram
1.1 CORE
The MC68EC000 core in the MC68EZ328 is an updated implementation of the M68000
32-bit microprocessor architecture. The main features of the core are:
¥ Low power, static HCMOS implementation
¥ 32-bit address bus and 16-bit data bus
¥ Sixteen 32-bit data and address registers
¥ 56 powerful instruction types that support high-level development languages
¥ 14 addressing modes and five main data types
¥ Seven priority levels for interrupt control
The core is completely code-compatible with other members of the M68000 families, which
means it has access to a broad base of established real-time kernels, operating systems,
languages, applications, and development tools.
1.1.1 Core Programming Model
The core has 32-bit registers and a 32-bit program counter, which are shown in Figure 1-2.
The first eight registers (D7ÐD0) are data registers that are used for byte (8-bit), word
(16-bit), and long-word (32-bit) operations. When using the data registers to manipulate
data, they affect the status register (SR). The next seven registers (A6ÐA0) and the user
1-2
MC68EZ328 USERÕS MANUAL
MOTOROLA
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