CY7C1297A View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1297A Datasheet PDF : 13 Pages
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CY7C1297A/
GVT7164B18
Truth Table[2, 3, 4, 5, 6, 7, 8]
Operation
Address
Used CE CE2 CE2 ADSP ADSC ADV WRITE OE
Deselected Cycle, Power Down None H X X
X
L
X
X
X
Deselected Cycle, Power Down None L X L
L
X
X
X
X
Deselected Cycle, Power Down None L H X
L
X
X
X
X
Deselected Cycle, Power Down None L X L
H
L
X
X
X
Deselected Cycle, Power Down None L H X
H
L
X
X
X
Read Cycle, Begin Burst
External L L H
L
X
X
X
L
Read Cycle, Begin Burst
External L L H
L
X
X
X
H
Write Cycle, Begin Burst
External L L H
H
L
X
L
X
Read Cycle, Begin Burst
External L L H
H
L
X
H
L
Read Cycle, Begin Burst
External L L H
H
L
X
H
H
Read Cycle, Continue Burst
Next
XX X
H
H
L
H
L
Read Cycle, Continue Burst
Next
XX X
H
H
L
H
H
Read Cycle, Continue Burst
Next H X X
X
H
L
H
L
Read Cycle, Continue Burst
Next H X X
X
H
L
H
H
Write Cycle, Continue Burst
Next
XX X
H
H
L
L
X
Write Cycle, Continue Burst
Next H X X
X
H
L
L
X
Read Cycle, Suspend Burst
Current X X X
H
H
H
H
L
Read Cycle, Suspend Burst
Current X X X
H
H
H
H
H
Read Cycle, Suspend Burst
Current H X X
X
H
H
H
L
Read Cycle, Suspend Burst
Current H X X
X
H
H
H
H
Write Cycle, Suspend Burst
Current X X X
H
H
H
L
X
Write Cycle, Suspend Burst
Current H X X
X
H
H
L
X
CLK
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
Partial Truth Table for Read/Write
Function
GW
BWE
WEH
WEL
Read
H
H
X
X
Read
H
L
H
H
Write one byte
H
L
L
H
Write all bytes
H
L
L
L
Write all bytes
L
X
X
X
Notes:
2. X means “don’t care.” H means logic HIGH. L means logic LOW. WRITE = L means [BWE + WEL*WEH]*GW equals LOW. WRITE = H means
[BWE + WEL*WEH]*GW equals HIGH.
3. WEL enables Write to DQ1–DQ8 and DQP1. WEH enables Write to DQ9–DQ16 and DQP2.
4. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
5. Suspending burst generates wait cycle.
6. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time plus High-Z time for OE and staying HIGH
throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW along with chip being selected always initiates a Read cycle at the L–H edge of CLK. A Write cycle can be performed by setting WRITE LOW for
the CLK L–H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification.
Document #: 38-05204 Rev. *A
Page 5 of 13
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