GDC21D601 View Datasheet(PDF) - Hyundai Micro Electronics

Part Name

Description

Manufacturer

GDC21D601

32-Bit RISC MCU

Hyundai Micro Electronics 

GDC21D601

Section 4. DRAM Controller

1. General Description

The DRAM controller interfaces the AMBA Advanced System Bus (ASB) to external DRAM memory banks. The

DRAM controller provides the following features:

• Up to two banks of DRAM support.

• Fast page-mode sequential access support.

• EDO DRAM support

• Word, Half-word and Byte transaction support.

• Little / Big Endian Format support.

• DRAM refresh controller using CAS-before-RAS (CBR) refresh mode.

• Programmable refresh rate.

• Power-down mode where all DRAM accesses (including self-refresh) are disabled.

• Programmable DRAM timing control.

• Row/column addresses multiplexes according to DRAM capacity.

Chip PAD

DRAM Controller

nDRAMWE

nDRAMOE

nRAS[1:0]

nCAS[3:0]

nCASFB[3:0]

Main State Machine

&

Control

Refresh

Timer & Controller

ASB Interface

&

Address Generator

EBI Signal Control

ASB Bus

BCLK

PDREQ

PDACK

DSELDRAM

DSELREG

BnRES

BLAST

BERROR

BWAIT

BWRITE

BSIZE[1:0]

BA[29:0]

BD[31:0]

Aout[23:0]

DataOut[31:0]

DataIn[31:0]

nOutEn[3:0]

Lat mux

Lat mux

mux Lat

BD[31:0]

Figure 1. DRAM Controller Module Block Diagram

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