AD5532(2000) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD5532 Datasheet PDF : 16 Pages
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AD5532
TIMING CHARACTERISTICS
PARALLEL INTERFACE
Parameter1, 2
Limit at TMIN, TMAX
(A Version)
Unit
t1
0
t2
0
t3
50
t4
50
t5
20
t6
0
ns min
ns min
ns min
ns min
ns min
ns min
NOTES
1See Interface Timing Diagram.
2Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
Conditions/Comments
CS to WR Setup Time
CS to WR Hold Time
CS Pulsewidth Low
WR Pulsewidth Low
A4–A0, CAL, OFFS_SEL to WR Setup Time
A4–A0, CAL, OFFS_SEL to WR Hold Time
SERIAL INTERFACE
Parameter1, 2
Limit at TMIN, TMAX
(A Version)
Unit
Conditions/Comments
fCLKIN3
14
t1
28
t2
28
t3
10
t4
50
t5
10
t6
5
t7
5
t84
20
t94
60
t10
400
t11
400
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
SCLK Frequency
SCLK High Pulsewidth
SCLK Low Pulsewidth
SYNC Falling Edge to SCLK Falling Edge Setup Time
SYNC Low Time
DIN Setup Time
DIN Hold Time
SYNC Falling Edge to SCLK Rising Edge Setup Time
SCLK Rising Edge to DOUT Valid
SCLK Falling Edge to DOUT High Impedance
10th SCLK Falling Edge to SYNC Falling Edge for Readback
24th SCLK Falling Edge to SYNC Falling Edge for DAC Mode Write
NOTES
1See Serial Interface Timing Diagrams.
2Guaranteed by design and characterization, not production tested.
3In SHA mode the maximum SCLK frequency is 20 MHz and the minimum pulsewidth is 20 ns.
4These numbers are measured with the load circuit of Figure 2.
Specifications subject to change without notice.
PARALLEL INTERFACE TIMING DIAGRAMS
CS
WR
A4–A0, CAL,
OFFS SEL
Figure 1. Parallel Write (SHA Mode Only)
TO
OUTPUT
PIN
200A
IOL
CL
50pF
200A
IOH
1.6V
Figure 2. Load Circuit for DOUT Timing Specifications
–4–
REV. 0
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