CY7C1327B-100BGI View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1327B-100BGI Datasheet PDF : 17 Pages
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CY7C1327B
Pin Configurations (continued)
119-Ball BGA
1
2
3
4
5
6
7
A
VDDQ
A
B
NC
CE2
C
NC
A
D
DQb
NC
E
NC
DQb
F
VDDQ
NC
G
NC
DQb
H
DQb
NC
J
VDDQ
VDD
K
NC
DQb
L
DQb
NC
M
VDDQ
DQb
N
DQb
NC
A
A
A
VSS
VSS
VSS
BWb
VSS
NC
VSS
Vss
VSS
VSS
ADSP
ADSC
VDD
NC
CE1
OE
ADV
GW
VDD
CLK
NC
BWE
A1
A
A
A
VSS
VSS
VSS
Vss
VSS
NC
VSS
BWa
VSS
VSS
A
CE3
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
VDDQ
NC
NC
NC
DQa
VDDQ
DQa
NC
VDDQ
DQa
NC
VDDQ
NC
P
NC
DQPb
VSS
A0
VSS
NC
DQa
R
NC
A
MODE
VDD
VSS
A
NC
T
NC
A
A
NC
A
A
ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
Pin Definitions
Name
A[17:0]
BW[1:0]
GW
BWE
CLK
CE1
CE2
CE3
OE
ADV
ADSP
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Input-
Synchronous
Input-
Synchronous
Description
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the
CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the
2-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW[1:0] and BWE).
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE3 to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE2 to select/deselect the device.
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
Advance Input Signal, sampled on the rising edge of CLK. When asserted, it automatically incre-
ments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A[17:0]
is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
Document #: 38-05140 Rev. **
Page 3 of 17
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