CY7C1327G(2006) View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1327G Datasheet PDF : 18 Pages
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Truth Table[2, 3, 4, 5, 6]
Next Cycle Add. Used CE1 CE2 CE3
Unselected
None
H
X
X
Unselected
None
L
X
H
Unselected
None
L
L
X
Unselected
None
L
X
H
Unselected
None
L
L
X
Begin Read
External
L
H
L
Begin Read
External
L
H
L
Continue Read
Next
X
X
X
Continue Read
Next
X
X
X
Continue Read
Next
H
X
X
Continue Read
Next
H
X
X
Suspend Read Current
X
X
X
Suspend Read Current
X
X
X
Suspend Read Current
H
X
X
Suspend Read Current
H
X
X
Begin Write
Current
X
X
X
Begin Write
Current
H
X
X
Begin Write
External
L
H
L
Continue Write
Next
X
X
X
Continue Write
Next
H
X
X
Suspend Write Current
X
X
X
Suspend Write Current
H
X
X
ZZ “Sleep”
None
X
X
X
Truth Table for Read/Write[2]
Function
Read
Read
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Bytes B, A
Write All Bytes
Write All Bytes
ZZ ADSP ADSC ADV
L
X
L
X
L
L
X
X
L
L
X
X
L
H
L
X
L
H
L
X
L
L
X
X
L
H
L
X
L
H
H
L
L
H
H
L
L
X
H
L
L
X
H
L
L
H
H
H
L
H
H
H
L
X
H
H
L
X
H
H
L
H
H
H
L
X
H
H
L
H
H
X
L
H
H
H
L
X
H
H
L
H
H
H
L
X
H
H
H
X
X
X
GW
BWE
H
H
H
L
H
L
H
L
H
L
H
L
L
X
CY7C1327G
OE
DQ WRITE
X
Tri-State
X
X
Tri-State
X
X
Tri-State
X
X
Tri-State
X
X
Tri-State
X
X
Tri-State
X
X
Tri-State
H
H
Tri-State
H
L
DQ
H
H
Tri-State
H
L
DQ
H
H
Tri-State
H
L
DQ
H
H
Tri-State
H
L
DQ
H
X
Tri-State
L
X
Tri-State
L
X
Tri-State
L
X
Tri-State
L
X
Tri-State
L
X
Tri-State
L
X
Tri-State
L
X
Tri-State
X
BWB
X
H
H
L
L
L
X
BWA
X
H
L
H
L
L
X
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BWA, BWB) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BWA, BWB),
BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: B]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05519 Rev. *F
Page 7 of 18
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