CY7C1327G-250AXI View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1327G-250AXI Datasheet PDF : 18 Pages
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PRELIMINARY
CY7C1327G
Switching Characteristics Over the Operating Range[14, 15]
250 MHz 225 MHz 200 MHz 166 MHz 133 MHz 100 MHz
Parameter
Description
tPOWER
VDD(Typical) to the first[10]
Clock
tCYC
Clock Cycle Time
tCH
Clock HIGH
tCL
Clock LOW
Output Times
tCO
Data Output Valid After CLK
Rise
Min. Max Min. Max Min. Max Min. Max Min. Max Min. Max Unit
1
1
1
1
1
1
ms
4.0
4.4
5.0
6.0
7.5
10
ns
1.7
2.0
2.0
2.5
3.0
3.5
ns
1.7
2.0
2.0
2.5
3.0
3.5
ns
2.6
2.6
2.8
3.5
4.0
4.5 ns
tDOH
tCLZ
tCHZ
tOEV
tOELZ
Data Output Hold After CLK
Rise
Clock to Low-Z[11, 12, 13]
Clock to High-Z[11, 12, 13]
1.0
1.0
1.0
1.5
1.5
1.5
ns
0
0
0
0
0
0
ns
2.6
2.6
2.8
3.5
4.0
4.5 ns
OE LOW to Output Valid
2.6
2.6
2.8
3.5
4.5
4.5 ns
OE LOW to Output Low-Z[11, 0
0
0
0
0
0
ns
12, 13]
tOEHZ
OE HIGH to Output High-Z[11,
12, 13]
2.6
2.6
2.8
3.5
4.0
4.5 ns
Set-up Times
tAS
Address Set-up Before CLK 1.2
1.2
1.2
1.5
1.5
1.5
ns
Rise
tADS
ADSC, ADSP Set-up Before 1.2
1.2
1.2
1.5
1.5
1.5
ns
CLK Rise
tADVS
ADV Set-up Before CLK Rise 1.2
1.2
1.2
1.5
1.5
1.5
ns
tWES
GW,
CLK
BWE,
Rise
BWX
Set-up
Before
1.2
1.2
1.2
1.5
1.5
1.5
ns
tDS
Data Input Set-up Before CLK 1.2
1.2
1.2
1.5
1.5
1.5
ns
Rise
tCES
Chip Enable Set-Up Before 1.2
1.2
1.2
1.5
1.5
1.5
ns
CLK Rise
Hold Times
tAH
Address Hold After CLK Rise 0.3
0.5
0.5
0.5
0.5
0.5
ns
tADH
ADSP , ADSC Hold After CLK 0.3
0.5
0.5
0.5
0.5
0.5
ns
Rise
tADVH
ADV Hold After CLK Rise
0.3
0.5
0.5
0.5
0.5
0.5
ns
tWEH
GW,BWE, BWX Hold After
0.3
0.5
0.5
0.5
0.5
0.5
ns
CLK Rise
tDH
Data Input Hold After CLK 0.3
0.5
0.5
0.5
0.5
0.5
ns
Rise
tCEH
Chip Enable Hold After CLK 0.3
0.5
0.5
0.5
0.5
0.5
ns
Rise
Shaded areas contain advance information.
Notes:
10. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation
can be initiated.
11. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
12. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
13. This parameter is sampled and not 100% tested.
14. Timing references level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V on all data sheets.
15. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05519 Rev. *A
Page 10 of 18
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