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CY7C1327G-200AXI View Datasheet(PDF) - Cypress Semiconductor

Part Name
Description
Manufacturer
CY7C1327G-200AXI
Cypress
Cypress Semiconductor Cypress
CY7C1327G-200AXI Datasheet PDF : 18 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
PRELIMINARY
CY7C1327G
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
DC Voltage Applied to Outputs
in tri-state ............................................ –0.5V to VDDQ + 0.5V
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
VDD
0°C to +70°C 3.3V –5%/+10%
–40°C to +85°C
VDDQ
2.5V –5%
to VDD
DC Input Voltage....................................–0.5V to VDD + 0.5V
Electrical Characteristics Over the Operating Range [7, 8]
Parameter
Description
Test Conditions
Min.
VDD
VDDQ
VOH
VOL
VIH
VIL
IX
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[7]
Input LOW Voltage[7]
Input Load Current
except ZZ and MODE
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
GND VI VDDQ
3.135
2.375
2.4
2.0
2.0
1.7
–0.3
–0.3
–5
Input Current of MODE Input = VSS
–30
Input = VDD
Input Current of ZZ
Input = VSS
–5
Input = VDD
IOZ
Output Leakage Current GND VI VDDQ, Output Disabled
–5
IDD
VDD Operating Supply VDD = Max.,
Current
IOUT = 0 mA,
f = fMAX =
1/tCYC
4-ns cycle,250MHz
4.4-ns cycle,225MHz
5-ns cycle,200MHz
6-ns cycle,166MHz
7.5-ns cycle,133MHz
10-ns cycle,100MHz
ISB1
Automatic CE
VDD = Max, Device
4-ns cycle,250MHz
Power-down
Current—TTL Inputs
Deselected, VIN VIH or
VIN VIL
f = fMAX = 1/tCYC
4.4-ns cycle,225MHz
5-ns cycle,200MHz
6-ns cycle,166MHz
7.5-ns cycle,133MHz
10-ns cycle,100MHz
ISB2
Automatic CE
VDD = Max, Device
Power-down
Deselected, VIN 0.3V or
Current—CMOS Inputs VIN > VDDQ – 0.3V, f = 0
All speeds
Shaded areas contain advance information.
Notes:
7. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2).
8. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD.
Max. Unit
3.6
V
VDD
V
V
V
0.4
V
0.4
V
VDD + 0.3V V
VDD + 0.3V V
0.8
V
0.7
V
5
µA
µA
5
µA
µA
30
µA
5
µA
325 mA
290 mA
265 mA
240 mA
225 mA
205 mA
120 mA
115 mA
110 mA
100 mA
90
mA
80
mA
40
mA
Document #: 38-05519 Rev. *A
Page 8 of 18

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