CY7C135 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

CY7C135

4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores

Cypress Semiconductor 

CY7C135

CY7C1342

Switching Waveforms (continued)

Semaphore Read After Write Timing, Either Side (CY7C1342 only)[19]

A0–A2

VALID ADDRESS

tAA

VALID ADDRESS

tOHA

SEM

tAW

tSCE

tHA

tSOP

tACE

I/O0

R/W

OE

tSD

DATAINVALID

tSA

tPWE

tHD

DATAOUT VALID

WRITE CYCLE

tSWRD

tSOP

tDOE

READ CYCLE

Timing Diagram of Semaphore Contention (CY7C1342 only)[20, 21, 22]

A0L–A2L

MATCH

R/WL

SEML

A0R–A2R

tSPS

MATCH

R/WR

SEMR

Notes:

19. CE = HIGH for the duration of the above timing (both write and read cycle).

20. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.

21. Semaphores are reset (available to both ports) at cycle start.

22. If tSPS is violated, it is guaranteed that only one side will gain access to the semaphore.

Document #: 38-06038 Rev. *C

Page 8 of 12

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