CY7C1345G-133AXI View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1345G-133AXI Datasheet PDF : 17 Pages
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PRELIMINARY
CY7C1345G
Thermal Resistance[10]
Parameter
ΘJA
ΘJC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard
test methods and procedures for
measuring thermal impedance,
per EIA / JESD51.
TQFP Package
TBD
TBD
BGA Package Unit
TBD
°C/W
TBD
°C/W
Capacitance[10]
Parameter
CIN
CCLK
CI/O
Description
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
AC Test Loads and Waveforms
Test Conditions TQFP Package BGA Package Unit
TA = 25°C, f = 1 MHz,
5
VDD = 3.3V.
VDDQ = 3.3V
5
5
5
pF
5
pF
7
pF
3.3V I/O Test Load
OUTPUT
Z0 = 50Ω
3.3V
OUTPUT
RL = 50Ω
5 pF
VT = 1.5V
(a)
INCLUDING
JIG AND
SCOPE
2.5V I/O Test Load
OUTPUT
2.5V
Z0 = 50Ω
OUTPUT
RL = 50Ω
5 pF
VT = 1.25V
INCLUDING
JIG AND
(a)
SCOPE
R = 317Ω
R = 351Ω
VDDQ
GND
ALL INPUT PULSES
10%
90%
≤ 1ns
90%
10%
≤ 1ns
(b)
(c)
R = 1667Ω
R =1538Ω
VDDQ
GND
ALL INPUT PULSES
10%
90%
≤ 1ns
90%
10%
≤ 1ns
(b)
(c)
Switching Characteristics Over the Operating Range [15, 16]
133 MHz
117 MHz
100 MHz
Parameter
tPOWER
Clock
Description
VDD(Typical) to the first Access[11]
Min. Max. Min. Max. Min. Max. Unit
1
1
1
ms
tCYC
tCH
tCL
Output Times
Clock Cycle Time
Clock HIGH
Clock LOW
7.5
8.5
10
ns
2.5
3.0
4.0
ns
2.5
3.0
4.0
ns
tCDV
Data Output Valid After CLK Rise
6.5
7.5
8.0 ns
tDOH
tCLZ
Data Output Hold After CLK Rise
Clock to Low-Z[12, 13, 14]
2.0
2.0
2.0
ns
0
0
0
ns
Notes:
10. Tested initially and after any design or process change that may affect these parameters.
11. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation
can be initiated.
12. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
13. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
14. This parameter is sampled and not 100% tested.
15. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
16. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05517 Rev. *A
Page 9 of 17
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