CY7C1350G(2004) View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1350G Datasheet PDF : 15 Pages
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PRELIMINARY
Pin Configuration (continued)
119-Ball Bump BGA
1
2
3
4
5
6
7
A
VDDQ
A
A
NC / 18M
A
A
VDDQ
B
NC
CE2
A
ADV/LD
A
CE3
NC
C
NC
A
A
VDD
A
A
NC
D
DQC
DQPC
VSS
NC
VSS
DQPB
DQB
E
DQC
DQC
VSS
F
VDDQ
DQC
VSS
CE1
OE
VSS
DQB
DQB
VSS
DQB
VDDQ
G
DQC
DQC
BWC NC / 9M BWB
DQB
DQB
H
DQC
DQC
VSS
WE
VSS
DQB
DQB
J
VDDQ
VDD
VSS
VDD
VSS
VDD
VDDQ
K
DQD
DQD
VSS
CLK
VSS
DQA
DQA
L
DQD
DQD
BWD
M
VDDQ
DQD
VSS
N
DQD
DQD
VSS
P
DQD
DQPD
VSS
NC
CEN
A1
A0
BWA
VSS
VSS
VSS
DQA
DQA
DQA
DQPA
DQA
VDDQ
DQA
DQA
R
NC
A
MODE
VDD
T
NC NC / 72M A
A
NC
A
NC
A NC / 36M ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
CY7C1350G
Pin Definitions
Name
A0, A1, A
BW[A:D]
WE
ADV/LD
CLK
CE1
CE2
CE3
OE
CEN
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Input-
Synchronous
Description
Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
of the CLK. A[1:0] are fed to the two-bit burst counter.
Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
the rising edge of CLK.
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input. Used to advance the on-chip address counter or load a new address. When
HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new
address can be loaded into the device for an access. After being deselected, ADV/LD should be
driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.
Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block
inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE
is masked during the data portion of a write sequence, during the first clock when emerging from
a deselected state, when the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the
SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
Document #: 38-05524 Rev. *A
Page 3 of 15
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