CY7C1350G(2004) View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1350G Datasheet PDF : 15 Pages
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PRELIMINARY
CY7C1350G
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V
DC Voltage Applied to Outputs
in tri-state ..................................................−0.5V to VDDQ + 0.5V
DC Input Voltage ....................................... −0.5V to VDD + 0.5V
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Com’l
Ind’l
Ambient
Temperature (TA)
0°C to +70°C
−40°C to +85°C
VDD
3.3V – 5% +10%
VDDQ
2.5V – 5%
to VDD
Electrical Characteristics Over the Operating Range [10, 11]
Parameter
Description
Test Conditions
VDD
VDDQ
VOH
VOL
VIH
VIL
IX
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[10]
Input LOW Voltage[10]
Input Load Current
except ZZ and MODE
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
GND ≤ VI ≤ VDDQ
Input Current of MODE Input = VSS
Input = VDD
Input Current of ZZ
Input = VSS
Input = VDD
IOZ
Output Leakage
GND ≤ VI ≤ VDDQ, Output Disabled
Current
IDD
VDD Operating Supply VDD = Max., IOUT = 0 mA,
Current
f = fMAX = 1/tCYC
4-ns cycle, 250 MHz
4.4-ns cycle, 225 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100MHz
ISB1
Automatic CE
VDD = Max, Device Deselected,
4-ns cycle, 250 MHz
Power-Down
VIN ≥ VIH or VIN ≤ VIL
4.4-ns cycle, 225 MHz
Current—TTL Inputs f = fMAX = 1/tCYC
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
ISB2
Automatic CE
VDD = Max, Device Deselected, All speeds
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V, f = 0
Current—CMOS Inputs
Shaded areas contain advance information.
Notes:
10. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2).
11. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Min. Max. Unit
3.135
3.6
V
2.375
VDD
V
2.4
V
2.0
V
0.4
V
0.4
V
2.0 VDD + 0.3V V
1.7 VDD + 0.3V V
–0.3
0.8
V
–0.3
0.7
V
−5
5
µA
−30
µA
5
µA
−5
µA
30
µA
−5
5
µA
325
mA
290
mA
265
mA
240
mA
225
mA
205
mA
120
mA
115
mA
110
mA
100
mA
90
mA
80
mA
40
mA
Document #: 38-05524 Rev. *A
Page 7 of 15
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