CY7C1352G(2004) View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1352G Datasheet PDF : 13 Pages
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PRELIMINARY
CY7C1352G
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive for
the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
00
01
10
01
00
11
10
11
00
11
10
01
Fourth
Address
A1, A0
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
10
11
00
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
00
01
10
Truth Table [2, 3, 4, 5, 6, 7, 8]
Operation
Deselect Cycle
Address
Used
None
CE ZZ ADV/LD WE BWx OE CEN
HL
L
X XX L
CLK
DQ
L-H tri-state
Continue Deselect Cycle
None
XL
H
X X X L L-H tri-state
Read Cycle (Begin Burst)
External
LL
L
H X L L L-H Data Out (Q)
Read Cycle (Continue Burst)
Next
XL
H
X X L L L-H Data Out (Q)
NOP/Dummy Read (Begin Burst)
External
LL
L
H X H L L-H tri-state
Dummy Read (Continue Burst)
Next
XL
H
X X H L L-H tri-state
Write Cycle (Begin Burst)
External
LL
L
L L X L L-H Data In (D)
Write Cycle (Continue Burst)
Next
XL
H
X L X L L-H Data In (D)
NOP/WRITE ABORT (Begin Burst) None
LL
L
L H X L L-H tri-state
WRITE ABORT (Continue Burst)
Next
XL
H
X H X L L-H tri-state
IGNORE CLOCK EDGE (Stall)
Current
XL
X
X X X H L-H –
SNOOZE MODE
None
XH
X
XXXX
X tri-state
Notes:
2. X=”Don't Care.” H= Logic HIGH, L =Logic LOW. CE stands for ALL Chip Enables active. BWX = L signifies at least one Byte Write Select is active, BWX = Valid
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
3. Write is defined by BW[A:B], and WE. See Write Cycle Descriptions table.
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:B] = tri-state when OE
is inactive or when the device is deselected, and DQs and DQP[A:B] = data when OE is active.
Document #: 38-05514 Rev. *A
Page 5 of 13
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