CY7C1353B View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1353B Datasheet PDF : 15 Pages
| |||
PRELIMINARY
CY7C1353B
Pin Configurations (continued)
119-Ball BGA
1
2
3
4
5
6
7
A
VDDQ
A
A
ADSP
A
A
VDDQ
B
NC
CE2
A
ADSC
A
CE3
NC
C
NC
A
A
VDD
A
A
NC
D
DQc
DQPc
VSS
NC
VSS
DQPb
DQb
E
DQc
DQc
VSS
CE1
VSS
DQb
DQb
F
VDDQ
DQc
VSS
OE
VSS
DQb
VDDQ
G
DQc
DQc
BWc
ADV
BWb
DQb
DQb
H
DQc
DQc
VSS
GW
VSS
DQb
DQb
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
DQd
DQd
VSS
CLK
VSS
DQa
DQa
L
DQd
DQd
BWd
NC
BWa
DQa
DQa
M
VDDQ
DQd
VSS
BWE
VSS
DQa
VDDQ
N
DQd
DQd
VSS
A1
VSS
DQa
DQa
P
DQd
DQPd
VSS
A0
VSS
DQPa
DQa
R
NC
A
MODE
VDD
VDD
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Pin Definitions
Pin Number
80, 50−44,
81−82, 99–
100, 32−37
94, 93
Name
A[17:0]
I/O
Input-
Synchronous
BWS[1:0] Input-
Synchronous
88
WE
Input-
Synchronous
85
ADV/LD Input-
Synchronous
89
CLK
Input-Clock
98
CE1
Input-
Synchronous
97
CE2
Input-
Synchronous
92
CE3
Input-
Synchronous
óIntroduction
Description
Address Inputs used to select one of the 262,144 address locations. Sampled at
the rising edge of the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWS0 controls DQ[7:0] and DP0, BWS1
controls DQ[15:8] and DP1. See Write Cycle Description table for details.
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new
address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2, and CE3 to select/deselect the device.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE and CE2 to select/deselect the device.
Document #: 38-05266 Rev. **
Page 3 of 15
Share Link: 