CY7C1353B View Datasheet(PDF) - Cypress Semiconductor
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CY7C1353B Datasheet PDF : 15 Pages
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PRELIMINARY
CY7C1353B
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs (A[17:0]) is
latched into the Address Register and presented to the mem-
ory core and control logic. The control logic determines that a
read access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 7.5
ns (117-MHz device) provided OE is active LOW. After the first
clock of the read access the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be three-stated
immediately.
Burst Read Accesses
The CY7C1353B has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enable inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to A[17:0] is loaded
into the Address Register. The write signals are latched into
the Control Logic block. The data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ[15:0] and
DP[1:0].
On the next clock rise the data presented to DQ[15:0] and
DP[1:0] (or a subset for byte write operations, see Write Cycle
Description table for details) inputs is latched into the device
and the write is complete. Additional accesses
(Read/Write/Deselect) can be initiated on this cycle.
The data written during the Write operation is controlled by
BWS[1:0] signals. The CY7C1353B provides byte write capa-
bility that is described in the Write Cycle Description table.
Asserting the Write Enable input (WE) with the selected Byte
Write Select (BWS[1:0]) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write mecha-
nism has been provided to simplify the write operations. Byte
write capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to sim-
ple byte write operations.
Because the CY7C1353B is a common I/O device, data should
not be driven into the device while the outputs are active. The
Output Enable (OE) can be deasserted HIGH before present-
ing data to the DQ[15:0] and DP[1:0] inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ[15:0]
and DP[1:0].are automatically three-stated during the data por-
tion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1353B has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial ad-
dress, as described in the Single Write Access section above.
When ADV/LD is driven HIGH on the subsequent clock rise,
the Chip Enables (CE1, CE2, and CE3) and WE inputs are
ignored and the burst counter is incremented. The correct
BWS[1:0] inputs must be driven in each cycle of the burst write
in order to write the correct bytes of data.
Document #: 38-05266 Rev. **
Page 5 of 15
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