CY7C1353B View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1353B Datasheet PDF : 15 Pages
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PRELIMINARY
CY7C1353B
Switching Characteristics Over the Operating Range[11, 12, 13]
-117
-100
-66
-50
-40
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tCYC
FMAX
tCH
tCL
tAS
tAH
tCDV
tDOH
tCENS
tCENH
tWES
Clock Cycle Time
8.5
10
15.0
20.0
25.0
ns
Maximum Operating Frequency
117
100
66
50
40 MHz
Clock HIGH
1.9
1.9
5.0
6.0
7.0
ns
Clock LOW
1.9
1.9
5.0
6.0
7.0
ns
Address Set-Up Before CLK Rise 2.0
2.0
2.0
2.0
2.5
ns
Address Hold After CLK Rise
0.5
0.5
0.5
1.0
1.0
ns
Data Output Valid After CLK Rise
7.5
8.5
11
12.0
14.0 ns
Data Output Hold After CLK Rise 1.5
1.5
1.5
1.5
1.5
ns
CEN Set-Up Before CLK Rise
2.0
2.0
2.0
2.0
2.5
ns
CEN Hold After CLK Rise
0.5
0.5
0.5
1.0
1.0
ns
WE, BWS[1:0] Set-Up Before CLK 2.0
2.0
2.0
2.0
2.5
ns
Rise
tWEH
tALS
tALH
tDS
tDH
tCES
tCEH
tCHZ
tCLZ
tEOHZ
WE, BWS[1:0] Hold After CLK Rise 0.5
0.5
0.5
1.0
1.0
ns
ADV/LD Set-Up Before CLK Rise 2.0
2.0
2.0
2.0
2.5
ns
ADV/LD Hold after CLK Rise
0.5
0.5
0.5
1.0
1.0
ns
Data Input Set-Up Before CLK Rise 2.0
2.0
2.0
2.0
2.5
ns
Data Input Hold After CLK Rise
0.5
0.5
0.5
1.0
1.0
ns
Chip Select Set-Up
2.0
2.0
2.0
2.0
2.5
ns
Chip Select Hold After CLK Rise 0.5
0.5
0.5
1.0
1.0
ns
Clock to High-Z[10, 12, 13, 14]
1.5 4.2 1.5 5.0 1.5 5.0 1.5 5.0 1.5 5.0 ns
Clock to Low-Z[10, 12, 13, 14]
3.0
3.0
3.0
3.0
3.0
ns
OE HIGH to Output High-Z[10, 12,
13, 14]
4.2
5.0
6.0
7.0
8.0 ns
tEOLZ
OE LOW to Output Low-Z[10, 12, 13, 0
14]
0
0
0
0
ns
tEOV
OE LOW to Output Valid[12]
4.2
5.0
6.0
7.0
8.0 ns
Note:
12. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
13. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
14. This parameter is sampled and not 100% tested.
Document #: 38-05266 Rev. **
Page 9 of 15
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