CY7C1353G(2007) View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

CY7C1353G
(Rev.:2007)

4-Mbit (256K x 18) Flow-through SRAM with NoBL™ Architecture

Cypress Semiconductor 

CY7C1353G

Switching Waveforms

Read/Write Waveforms[19, 20, 21]

1

2 tCYC 3

4

5

6

7

8

9

10

CLK

tCENS tCENH

tCH tCL

CEN

tCES tCEH

CE

ADV/LD

WE

BW[A:B]

ADDRESS A1

A2

tAS tAH

A3

tCDV

tCLZ

A4

tDOH

A5

A6

A7

tOEV tCHZ

DQ

D(A1)

D(A2) D(A2+1)

tDS tDH

OE

COMMAND WRITE

WRITE

BURST

READ

D(A1)

D(A2)

WRITE

Q(A3)

D(A2+1)

Q(A3) Q(A4)

Q(A4+1)

D(A5)

tOEHZ

tDOH

tOELZ

Q(A6)

D(A7)

READ

Q(A4)

BURST

READ

Q(A4+1)

WRITE

D(A5)

READ

Q(A6)

WRITE DESELECT

D(A7)

DON’T CARE UNDEFINED

Notes:

19.For this waveform ZZ is tied low.

20.When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

21.Order of the Burst sequence is determined by the status of the MODE (0= Linear, 1= Interleaved). Burst operations are optional.

Document #: 38-05515 Rev. *E

Page 10 of 13

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