CY7C1353 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1353 Datasheet PDF : 13 Pages
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CY7C1353
dress, as described in the Single Write Access section above.
When ADV/LD is driven HIGH on the subsequent clock rise,
the chip enables (CE1, CE2, and CE3) and WE inputs are ig-
nored and the burst counter is incremented. The correct
BWS[1:0] inputs must be driven in each cycle of the burst write
in order to write the correct bytes of data.
Cycle Description Truth Table[1, 2, 3, 4, 5, 6]
Operation
Deselected
Address
used
External
ADV/
CE CEN LD
WE BWSx CLK
Comments
1
0
L
X
X
L-H
I/Os three-state following next rec-
ognized clock.
Suspend
-
X
1
X
X
X
L-H
Clock Ignored, all operations sus-
pended.
Begin Read
External
0
0
0
1
X
L-H
Address Latched.
Begin Write
External
0
0
0
0
Valid L-H
Address Latched, data presented
two valid clocks later.
Burst READ
Operation
Internal
X
0
1
X
X
L-H
Burst Read Operation. Previous
access was a Read operation. Ad-
dresses incremented internally in
conjunction with the state of Mode.
Burst WRITE
Operation
Internal
X
0
1
X
Valid L-H
Burst Write Operation. Previous
access was a Write operation. Ad-
dresses incremented internally in
conjunction with the state of Mode.
Bytes written are determined by
BWS[1:0].
Note:
1. X=Don't Care, 1=Logic HIGH, 0=Logic LOW, CE stands for ALL Chip Enables active. BWSx = 0 signifies at least one Byte Write Select is active, BWSx =
Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWS[1:0]. See Write Cycle Description table for details.
3. The DQ and DP pins are controlled by the current cycle and the OE signal.
4. CEN=1 inserts wait states.
5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
6. OE assumed LOW.
5
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