CY7C1357A View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

CY7C1357A

256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL™ Architecture

Cypress Semiconductor 

CY7C1357A

CY7C1355A

controller is moved to Update-IR state. The TAP instruction

sets for this device are listed in the following tables.

EXTEST

EXTEST is an IEEE 1149.1 mandatory public instruction. It is

to be executed whenever the instruction register is loaded with

all 0s. EXTEST is not implemented in this device.

The TAP controller does recognize an all-0 instruction. When

an EXTEST instruction is loaded into the instruction register,

the device responds as if a SAMPLE/PRELOAD instruction

has been loaded. There is one difference between two instruc-

tions. Unlike SAMPLE/PRELOAD instruction, EXTEST places

the device outputs in a High-Z state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the ID register when the controller is in

Capture-DR mode and places the ID register between the TDI

and TDO pins in Shift-DR mode. The IDCODE instruction is

the default instruction loaded in the instruction upon power-up

and at any time the TAP controller is placed in the test-logic

reset state.

SAMPLE-Z

If the High-Z instruction is loaded in the instruction register, all

output pins are forced to a High-Z state and the boundary scan

register is connected between TDI and TDO pins when the

TAP controller is in a Shift-DR state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction.

The PRELOAD portion of the command is not implemented in

this device, so the device TAP controller is not fully IEEE

1149.1-compliant.

When the SAMPLE/PRELOAD instruction is loaded in the

instruction register and the TAP controller is in the Capture-DR

state, a snap shot of the data in the device’s input and I/O

buffers is loaded into the boundary scan register. Because the

device system clock(s) are independent from the TAP Clock

(TCK), it is possible for the TAP to attempt to capture the input

and I/O ring contents while the buffers are in transition (i.e., in

a metastable state). Although allowing the TAP to sample

metastable inputs will not harm the device, repeatable results

can not be expected. To guarantee that the boundary scan

register will capture the correct value of a signal, the device

input signals must be stabilized long enough to meet the TAP

controller’s capture set up plus hold time (tCS plus tCH). The

device clock input(s) need not be paused for any other TAP

operation except capturing the input and I/O ring contents into

the boundary scan register.

Moving the controller to Shift-DR state then places the

boundary scan register between the TDI and TDO pins.

Because the PRELOAD portion of the command is not imple-

mented in this device, moving the controller to the Update-DR

state with the SAMPLE/PRELOAD instruction loaded in the

instruction register has the same effect as the Pause-DR

command.

BYPASS

When the BYPASS instruction is loaded in the instruction

register and the TAP controller is in the Shift-DR state, the

bypass register is placed between TDI and TDO. This allows

the board level scan path to be shortened to facilitate testing

of other devices in the scan path.

Document #: 38-05265 Rev. *A

Page 11 of 28

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