CY7C1357A View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

CY7C1357A

256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL™ Architecture

Cypress Semiconductor 

Functional Block Diagram 256Kx36[1]

ZZ

MODE

CEN

ADV/LD

WWEEN

BWa, BWb

BWc, BWd

CE, CE1, CE2,CE3

Input

Registers

A0, AA10,, SAA1, A

CLK

OE

CY7C1357A

CY7C1355A

Address

Control

Control Logic

Sel

Mux

Output Buffers

Functional Block Diagram 512Kx18[1]

ZZ

MODE

CEN

ADV/LD

WRE/WN

BWa, BWb

CE, CE1, CE2,CE3

Input

Registers

A0, AA10,S,AA1, A

CLK

OE

DQa-DQd

Address

Control

Control Logic

Sel

Mux

Output Buffers

DQa, DQb

Note:

1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.

Document #: 38-05265 Rev. *A

Page 2 of 28

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