CY7C1357A View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1357A
Cypress Semiconductor
CY7C1357A Datasheet PDF : 28 Pages
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CY7C1357A
CY7C1355A
Pin Descriptions (CY7C1355A)
256K × 36
TQFP Pins
256K × 36
PBGA Pins Name
Type
Description
37,
4P
A0,
36,
4N
A1,
32, 33, 34, 35, 2A, 3A, 5A, 6A, A
44, 45, 46, 47, 3B, 5B, 2C, 3C,
48, 49, 50, 81, 5C, 6C, 4G, 2R,
82, 83, 99, 100 6R, 3T, 4T, 5T
Input- Synchronous Address Inputs: The address register is triggered by
Synchronous a combination of the rising edge of CLK, ADV/LD LOW, CEN LOW
and true chip enables. A0 and A1 are the two least significant bits of
the address field and set the internal burst counter if burst cycle is
initiated.
93,
5L
BWa,
Input- Synchronous Byte Write Enables: Each nine-bit byte has its own
94,
5G
BWb, Synchronous active LOW byte write enable. On load write cycles (when WEN and
95,
3G
BWc,
ADV/LD are sampled LOW), the appropriate byte write signal (BWx)
96
3L
BWd
must be valid. The byte write signal must also be valid on each cycle
of a burst write. Byte write signals are ignored when WEN is sampled
HIGH. The appropriate byte(s) of data are written into the device one
cycle later. BWa controls DQa pins; BWb controls DQb pins; BWc
controls DQc pins; BWd controls DQd pins. BWx can all be tied LOW
if always doing a write to the entire 36-bit word.
87
4M
CEN
Input- Synchronous Clock Enable Input: When CEN is sampled HIGH, all
Synchronous other synchronous inputs, including clock are ignored and outputs
remain unchanged. The effect of CEN sampled HIGH on the device
outputs is as if the LOW-to-HIGH clock transition did not occur. For
normal operation, CEN must be sampled LOW at rising edge of clock.
88
4H
WEN
Input- Read Write: WEN signal is a synchronous input that identifies
Synchronous whether the current loaded cycle and the subsequent burst cycles
initiated by ADV/LD is a Read or Write operation. The data bus activity
for the current cycle takes place one clock cycle later.
89
4K
CLK
Input- Clock: This is the clock input to CY7C1355A. Except for OE, ZZ, and
Clock MODE, all timing references for the device are made with respect to
the rising edge of CLK.
98, 92
4E, 6B
CE1,
CE3
Input- Synchronous Active LOW Chip Enable: CE1 and CE3 are used with
Synchronous CE2 to enable the CY7C1355A. CE1 or CE3 sampled HIGH or CE2
sampled LOW, along with ADV/LD LOW at the rising edge of clock,
initiates a deselect cycle. The data bus will be High-Z one clock cycle
after chip deselect is initiated.
97
2B
CE2
Input- Synchronous Active High Chip Enable: CE2 is used with CE1 and
Synchronous CE3 to enable the chip. CE2 has inverted polarity but otherwise is
identical to CE1 and CE3.
86
4F
OE
Input
Asynchronous Output Enable: OE must be LOW to read data.
Asynchronous When OE is HIGH, the I/O pins are in high-impedance state. OE does
not need to be actively controlled for read and write cycles. In normal
operation, OE can be tied LOW.
85
4B
ADV/
Input- Advance/Load: ADV/LD is a synchronous input that is used to load
LD Synchronous the internal registers with new address and control signals when it is
sampled LOW at the rising edge of clock with the chip is selected.
When ADV/LD is sampled HIGH, then the internal burst counter is
advanced for any burst that was in progress. The external addresses
and WEN are ignored when ADV/LD is sampled HIGH.
31
3R
MODE
Input- Burst Mode: When MODE is HIGH or NC, the interleaved burst
Static sequence is selected. When MODE is LOW, the linear burst
sequence is selected. MODE is a static DC input.
64
7T
ZZ
Input- Sleep Enable: This active HIGH input puts the device in low power
Asynchronous consumption standby mode. For normal operation, this input has to
be either LOW or NC.
Document #: 38-05265 Rev. *A
Page 5 of 28
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