CY7C1357A View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1357A
Cypress Semiconductor
CY7C1357A Datasheet PDF : 28 Pages
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CY7C1357A
CY7C1355A
Pin Descriptions (CY7C1355A) (continued)
256K × 36
TQFP Pins
256K × 36
PBGA Pins
51, 52, 53, (a) 6P, 7P, 7N,
56–59, 62, 63 6N, 6M, 6L, 7L,
68, 69, 72–75,
6K, 7K,
78, 79, 80 (b) 7H, 6H, 7G,
1, 2, 3, 6–9, 12, 6G, 6F, 6E, 7E,
13
7D, 6D,
18, 19, 22–25, (c) 2D, 1D, 1E,
28, 29, 30 2E, 2F, 1G, 2G,
1H, 2H,
(d) 1K, 2K, 1L,
2L, 2M, 1N, 2N,
1P, 2P
38
2U
39
3U
43
4U
Name
DQa
DQb
DQc
DQd
TMS
TDI
TCK
Type
Description
Input/ Data Inputs/Outputs: Both the data input path and data output path
Output are registered and triggered by the rising edge of CLK. Byte “a” is
Synchronous DQa pins; Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is DQd
pins.
Input
IEEE 1149.1 test inputs: LVTTL-level inputs. If Serial Boundary Scan
(JTAG) is not used, these pins can be floating (i.e., No Connect) or
be connected to VCC.
42
5U
TDO
15, 16, 41, 65, 4C, 2J, 4J, 6J, VCC
91
4R
5, 10, 14, 17, 3D, 5D, 3E, 5E, VSS
21, 26, 40, 55, 3F, 5F, 3H, 5H,
60, 66, 67, 71, 3K, 5K, 3M, 5M,
76, 90
3N, 5N, 3P, 5P,
5R
4, 11, 20, 27, 54, 1A, 7A, 1F, 7F, VCCQ
61, 70, 77 1J, 7J, 1M, 7M,
1U, 7U
84
4A, 1B, 7B, 1C, NC
7C, 4D, 3J, 5J,
4L, 1R, 7R, 1T,
2T, 6T, 6U
Output
Power
Supply
IEEE 1149.1 test output: LVTTL-level output. If Serial Boundary
Scan (JTAG) is not used, these pins can be floating (i.e., No Connect).
Power Supply: +3.3V –5% and +5%.
Ground Ground: GND.
I/O Power Power Supply for the I/O circuitry.
Supply
–
No Connect: These signals are not internally connected. It can be
left floating or be connected to VCC or to GND.
Pin Descriptions (CY7C1357A)
512K × 18
TQFP Pins
37,
36,
32, 33, 34, 35, 44,
45, 46, 47, 48, 49,
50, 80, 81, 82, 83,
99, 100
93,
94,
Name
A0,
A1,
A
BWa,
BWb
87
CEN
Type
Input-
Synchronous
Description
Synchronous Address Inputs: The address register is triggered by a
combination of the rising edge of CLK, ADV/LD LOW, CEN LOW and true
chip enables. A0 and A1 are the two least significant bits of the address
field and set the internal burst counter if burst cycle is initiated.
Input-
Synchronous
Input-
Synchronous
Synchronous Byte Write Enables: Each nine-bit byte has its own active
low byte write enable. On load write cycles (when WEN and ADV/LD are
sampled LOW), the appropriate byte write signal (BWx) must be valid. The
byte write signal must also be valid on each cycle of a burst write. Byte
write signals are ignored when WEN is sampled HIGH. The appropriate
byte(s) of data are written into the device one cycle later. BWa controls
DQa pins; BWb controls DQb pins. BWx can all be tied LOW if always
doing write to the entire 18-bit word.
Synchronous Clock Enable Input: When CEN is sampled HIGH, all
other synchronous inputs, including clock are ignored and outputs remain
unchanged. The effect of CEN sampled HIGH on the device outputs is as
if the LOW-to-HIGH clock transition did not occur. For normal operation,
CEN must be sampled LOW at rising edge of clock.
Document #: 38-05265 Rev. *A
Page 6 of 28
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